Altera RAM-Based Shift Register Bedienungsanleitung PDF herunterladen (Seite 21)

May 2013 Altera Corporation RAM-Based Shift Register (ALTSHIFT_TAPS) Megafunction User Guide

3. Specifications

This chapter describes the prototypes, declarations, ports, and parameters of the

ALTSHIFT_TAPS megafunction. You can use the ports and parameters to customize

the ALTSHIFT_TAPS megafunction according to your application.

Verilog HDL Prototype for the ALTSHIFT_TAPS Megafunction

You can locate the following Verilog HDL prototype in the Verilog Design File (.v)

altera_mf.v in the <Quartus II installation directory>\eda\synthesis directory.

module altshift_taps

#( parameter intended_device_family = “unused”,

parameter number of taps = 1,

parameter power_up_state = “CLEARED”,

parameter taps_distance = 1,

parameter width = 1,

parameter lpm_type = “altshift_taps”,

parameter lpm_hint = “unused”)

( input wire aclr,

input wire clken,

input wire clock,

input wire [width-1:0] shiftin,

output wire [width-1:0] shiftout,

output wire [width*number_of_taps-1:0] taps)/*synthesis syn_black_box=1 */;

endmodule \\altshift_taps

VHDL Component Declaration for the ALTSHIFT_TAPS Megafunction

You can locate the following VHDL Design File (.vhd) altera_mf.vhd in the

<Quartus II installation directory>\libraries\bhdl\altera_mf directory.

component altshift_taps

generic (

intended_device_family : string := “unused”;

number_of_taps : natural;

power_up_state : string := “CLEARED”;

tap_distance : natural;

width : natural;

lpm_hint : string := “UNUSED”;

lpm_type : string := “altshift_taps”

);

port(

aclr : in std_logic := ‘0’;

clken : in std_logic := ‘1’;

clock : in std_logic;

shiftin: in std_logic_vector(width-1 downto 0);

shiftout : out std_logic_vector(width-1 downto 0);

taps : out std_logic_vector(width*number_of_taps-1 downto 0)

);

end component;

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