Altera RAM-Based Shift Register Bedienungsanleitung PDF herunterladen (Seite 17)

Chapter 2: Getting Started 2–11

Design Example: Shift Register with Taps

May 2013 Altera Corporation RAM-Based Shift Register (ALTSHIFT_TAPS) Megafunction User Guide

Figure 2–9 shows the first three data words written into the shift register chain, shifted

in the register chain, and the first data shown at the

taps0x

output.

At 5 ns, the

clken

signal is low and therefore no operation is executed. You can

consider 15 ns to be the first rising clock edge, as this is when the operation begins.

The first data

is shifted into the shift register as shown in Figure 2–10. All outputs

show

because no data is being shifted to any of the outputs.

At 25 ns and 35 ns, the second data

and the third data

are shifted into the shift

1 The existing data in the shift register chain are shifted right before the shift-in of new

data.

Figure 2–11 shows the content in the shift register chain at 35 ns. All of the outputs

show

except

taps0x

, which shows the first data,

Figure 2–9. First Three Data Written and Shifted in the Shift Register

Figure 2–10. Content of the Shift Register Chain at 15 ns

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 25 26

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Altera RAM-Based Shift Register Bedienungsanleitung Seite 17