Altera MAX 10 FPGA Bedienungsanleitung PDF herunterladen (Seite 48)

MAX 10 FPGA Configuration IP Core

Implementation Guides

2015.05.04

UG-M10CONFIG

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Altera Unique Chip ID IP Core

This section provides the guideline to implement the Altera Unique Chip ID IP Core.

Related Information

• Unique Chip ID on page 2-16

• Altera Unique Chip ID IP Core Ports on page 6-1

Instantiating the Altera Unique Chip ID IP Core

To instantiate the Altera Unique Chip ID IP Core, follow these steps:

1. On the Tools menu of the Quartus II software, click IP Catalog.

2. Under the Library category, expand the Basic Functions and Configuration Programming.

3. Select Altera Unique Chip ID and click Add, and enter your desired output file name

4. In the Save IP Variation dialog box:

• Set your IP variation filename and directory.

• Select IP variation file type.

5. Click Finish.

Resetting the Altera Unique Chip ID IP Core

To reset the Altera Unique Chip ID IP core, you must assert high to the reset signal for at least one clock

cycle. After you de-assert the reset signal, the Altera Unique Chip ID IP core re-reads the unique chip ID

of your device from the fuse ID block. The Altera Unique Chip ID IP core asserts the data_valid signal

after completing the operation.

Altera Dual Configuration IP Core

This section provides the guideline to implement the Altera Dual Configuration IP Core.

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of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any

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