Altera Low Latency Ethernet 10G MAC Bedienungsanleitung Seite 45
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Figure 3-19: PHY Configuration with 10GBASE-R Register Mode Enabled.
Figure shows a block diagram of the PHY configuration when operating in 10GBASE-R mode.
Transmitter 10G PCS
Receiver 10G PCS
Transmitter PMA
Receiver PMA
Parallel Clock (Recovered)
Parallel Clock (322+ MHz)
FPGA
Fabric
Register
Register
Frame Generator
CRC32
Generator
CRC32
Checker
64B/66B Encoder
and TX SM
64B/66B Decoder
and RX SM
Scrambler
De-Scrambler
Disparity Checker
Block Synchronizer
Frame Synchronizer
Disparity
Generator
TX Gear Box
RX Gear Box
Serializer
Deserializer
CDR
rx_serial_data
tx_serial_data
Parallel Clock
Serial Clock
Parallel and Serial Clock
BER
Monitor
Div 32
Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Serial Clock
(From the ×1 Clock Lines)
Central/ Local Clock Divider
Parallel and Serial Clocks
(Only from the Central Clock Divider)
CMU PLL
64-Bit Data
8-Bit Control
64-Bit Data
8-Bit Control
66
66 32
3266
Input Reference
Clock
64-Bit
Data
8-Bit
Control
fPLL
64-Bit
Data
8-Bit
Control
Related Information
Arria 10 Transceiver PHY User Guide
More information on how to configure the transceivers to implement 10GBASE-R functionality by using
the preset of the Arria 10 Transceivers Native PHY IP core.
XGMII Error Handling (Link Fault)
The LL Ethernet 10G MAC supports link fault generation and detection.
When the MAC RX receives a local fault, the MAC TX starts sending remote fault status (0x9c000002) on
the XGMII. If the packet transmission was in progress at the time, the remote fault bytes will override the
packet bytes until the fault condition ceases.
When the MAC RX receives a remote fault, the MAC TX starts sending IDLE bytes (0x07070707) on its
XGMII. If packet transmission was in progress at the time, the IDLE bytes will override the packet bytes
until the fault condition ceases.
The MAC considers the link fault condition has ceased if the client and the remote partner both receive
valid data in more than 127 columns.
UG-01144
2014.12.15
XGMII Error Handling (Link Fault)
3-23
Functional Description of LL Ethernet 10G MAC
Altera Corporation
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
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