Altera Low Latency Ethernet 10G MAC Bedienungsanleitung Seite 14
- Seite / 109
- Inhaltsverzeichnis
- LESEZEICHEN
Bewertet. / 5. Basierend auf Kundenbewertungen
Parameter Value Description
Number of PFC queues 2—8 Specify the number of PFC queues. This
parameter is only enabled if you turn Enable
priority-based flow control (PFC).
Enable unidirectional feature On, Off Turn on this option to enable unidirectional
feature as specified in the IEEE802.3 specifica‐
tion (Clause 66). This feature is only supported
in 10Gbps speed mode.
This parameter is not available if you turn on
the Enable 10GBASE-R register mode
parameter.
Enable 10GBASE-R register
mode
On, Off Turn on this option to enable 10GBASE-R
register mode on the transmit and receive
datapaths to further reduce the MAC and PHY
round-trip latency. In this mode, the MAC
datapaths must run at 322.265625 MHz. This
feature is only supported in 10Gbps speed
mode.
Enable supplementary
address
On, Off Turn on this option to enable supplementary
addresses. You must also set the EN_SUPP0/1/2/
3 bits in the rx_frame_control register to 1.
Enable statistics collection On, Off Turn on this option to collect statistics on the
transmit and receive datapaths.
Statistics counters Memory-based,
Register-based
Specify the implementation of the statistics
counters. When you turn on Statistics
collection, the default implementation of the
counters is Memory-based.
• Memory-based—selecting this option frees
up logic elements. The MAC IP core does
not clear memory-based counters after they
are read.
• Register-based—selecting this option frees
up the memory. The MAC IP core clears
register-based statistic counters after the
counters are read.
Enable time stamping
On, Off Turn on this option to enable time stamping on
the transmit and receive datapaths.
This parameter is not available if you turn on
the Enable 10GBASE-R register mode
parameter.
Enable PTP one-step clock
support
On, Off Turn on this option to enable 1-step time
stamping. This option is enabled only when
you turn on time stamping.
UG-01144
2014.12.15
Parameter Settings
2-5
Getting Started with LL Ethernet 10G MAC
Altera Corporation
Send Feedback
- Low Latency Ethernet 10G MAC 1
- Contents 2
- About LL Ethernet 10G MAC 5
- Features 6
- Release Information 7
- Resource Utilization 8
- TX and RX Latency 9
- Related Information 10
- Parameter Settings 13
- Parameter Value Description 13
- Generated Files 15
- Extension Description 15
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Altera Corporation 19
- Send Feedback 19
- Design Considerations 20
- Pseudo-Static CSR Fields 21
- Clock Crosser 21
- Dual Clock FIFO 22
- Subscribe 23
- Interfaces 24
- Interfaces Description 24
- Figure 3-2: Interface Signals 25
- Padding Bytes Insertion 26
- Address Insertion 26
- CRC-32 Insertion 27
- XGMII Encapsulation 28
- XGMII Transmission 29
- Unidirectional Feature 30
- TX Timing Diagrams 31
- RX Datapath 35
- Address Checking 36
- Frame Type Checking 36
- Length Checking 36
- Frame Length 37
- Payload Length 37
- Overflow Handling 38
- RX Timing Diagrams 38
- IEEE 802.3 Flow Control 39
- Pause Frame Reception 40
- Pause Frame Transmission 40
- Priority-Based Flow Control 41
- PFC Frame Reception 42
- PFC Frame Transmission 42
- Reset Requirements 42
- No Stage Steps 43
- Operating Mode PHY 44
- IEEE 1588v2 47
- Transmit Datapath 48
- Receive Datapath 49
- Frame Format 49
- PTP Packet over UDP/IPv4 50
- PTP Packet over UDP/IPv6 51
- 4 Octets 52
- Register Map 53
- Word Offset Purpose Variation 53
- (10-Gbps Ethernet MAC) 54
- (LL Ethernet 10G MAC) 54
- Register Access 56
- Access Definition 57
- Flow Control Registers 62
- Delay Device PMA Mode 76
- Latency MAC Configurations 76
- ECC Registers 76
- Statistics Registers 77
- Clock and Reset Signals 83
- Signal Operating 83
- Direction Width Description 83
- Unidirectional Signals 86
- Avalon-MM Programming Signals 86
- Avalon-ST Data Interfaces 87
- Avalon-ST Status Interface 90
- PHY-side Interfaces 94
- XGMII RX Signals 97
- GMII TX Signals 98
- GMII RX Signals 99
- MII TX Signals 99
- MII RX Signals 99
- 1588v2 Interfaces 100
- UG-01144 101
- 2014.12.15 101
- Additional Information 107
- Date Version Changes 108
Verwandte Produkte und Handbücher für Messgeräte Altera Low Latency Ethernet 10G MAC
(72 Seiten)© 2020, manymanuals.de. Alle Rechte vorbehalten. | 0.022 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Kommentare zu diesen Handbüchern