Altera JESD204B IP Bedienungsanleitung Seite 86
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requires a read-modify-write operation (read first, then write), in such a way that it modifies only the
appropriate bits in a register and not changing other bits.
In the design example, MIF approach is used to reconfigure the ATX PLL and transceiver channel in the
JESD204 IP core via the Transceiver Reconfiguration Controller. The number of reconfiguration interface
is determined by number of lanes (L) + number of TX_PLL (different number of TX_PLL for bonded and
non-bonded mode). Since the MIF approach reconfiguration for transceiver only supports non-bonded
mode, the number of TX_PLL is equal to number of lanes. The number of reconfiguration interface = 2 x
number of lanes (L).
The transceiver reconfiguration controller interfaces:
• MIF Reconfiguration Avalon-MM master interface—connects to the MIF ROM.
• Transceiver Reconfiguration interface—connects to the JESD204B IP core, which eventually connects
to the native PHY.
• Reconfiguration Management Avalon-MM slave interface—connects to the control unit.
Note: The transceiver reconfiguration controller is only used in Arria V and Stratix V devices. For Arria
10 devices, the control unit directly communicates with the transceiver in the JESD204B IP core
through the reconfig_avmm_* interface signals.
The following transceiver reconfiguration controller Avalon-MM operations are involved during data rate
reconfiguration.
Table 5-2: Transceiver Reconfiguration Controller Operation for Arria V and Stratix V Devices
Operation Avalon-MM
Interface Signal
Byte Address
Offset (6bits)
Bit Value
Write logical channel number reconfig_mgmt_* 0x38 [9:0] 0
Write MIF mode reconfig_mgmt_* 0x3A [3:2] 2'b00
Write 0 to streamer offset register reconfig_mgmt_* 0x3B [15:0] 0
Write MIF base address to streamer
data register
reconfig_mgmt_* 0X3C [31:0] *32'h1000
Initiate a write of all the above data reconfig_mgmt_* 0x3A [0] 1'b1
Write 1 to streamer offset register reconfig_mgmt_* 0x3B [15:0] 1
Write to streamer data register to set up
MIF streaming
reconfig_mgmt_* 0x3C [31:0] 3
Initiate a write of all the above data to
start streaming the MIF
reconfig_mgmt_* 0x3A [0] 1'b1
Read the busy bit to determine when
the write has completed
reconfig_mgmt_* 0x3A [8]
1: Busy
0: Operation
completed
Note: The above steps are repeated for the number of channels and followed by the number of TX_PLLs.
UG-01142
2015.05.04
Transceiver Reconfiguration Controller
5-5
JESD204B IP Core Design Guidelines
Altera Corporation
Send Feedback
- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
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