Altera JESD204B IP Bedienungsanleitung Seite 87
- Seite / 158
- Inhaltsverzeichnis
- LESEZEICHEN
Bewertet. / 5. Basierend auf Kundenbewertungen
For Arria 10 devices, the only Avalon-MM operation is a direct write to the transceiver register through
the reconfig_avmm_* interface at the JESD204B IP core. Every line in the MIF is
DPRIO_ADDR[25:16]+ BIT_MASK[15:8]+ DATA[7:0]. The control unit maps the
DPRIO_ADDR to reconfig_avmm_address and BIT_MASK '&' DATA to reconfig_avmm_data.
Related Information
• Altera Transceiver PHY IP Core User Guide
More information about the transceiver reconfiguration controller.
• Altera Arria 10 Transceiver PHY IP Core User Guide
Transceiver Reset Controller
The transceiver reset controller uses the Altera's Transceiver PHY Reset Controller IP Core to ensure a
reliable initialization of the transceiver. The reset controller has separate reset controls per channel to
handle synchronization of reset inputs, hysteresis of PLL locked status, and automatic or manual reset
recovery mode.
In this design example, the reset controller targets both the TX and RX channels. The TX PLL, TX
Channel, and RX Channel parameters are programmable to accommodate single and multiple (2)
JESD204B links.
Related Information
• Altera Transceiver PHY IP Core User Guide
More information about the Transceiver PHY Reset Controller IP Core.
• Arria V Device Handbook, Volume 2: Transceivers
More information about the device usage mode.
Pattern Generator
The pattern generator instantiates any supported generators and has an output multiplexer to select which
generated pattern to forward to the transport layer based on the test mode during run time. Additionally,
the pattern generator also supports run-time reconfiguration (downscale) on the number of converters
per device (M) & samples per converter per frame (S).
The pattern generator can be a parallel PRBS, alternate checkerboard, or ramp wave generator. The data
output bus width of the pattern generator is equivalent to the value of FRAMECLK_DIV × M × S × N.
The pattern generator includes a REVERSE_DATA parameter to control data arrangement at the output.
The default value of this parameter is 0.
• 0—no data rearrangement at the output of the generator.
• 1—data rearrangement at the output of the generator.
For example, when M=2, S=1, N=16, F1/F2_FRAMECLK_DIV=1, the input or output data width equals
to [31:0], with the following data arrangement:
0: {m1s0[31:16], m0s0[15:0]}
1: {m0s0[31:16], m1s0[15:0]}
Parallel PRBS Generator
PRBS generator circuits often consists of simple shift registers with feedback that serve as test sources for
serial data links. The output sequence is not truly random but repeats after 2
X
–1 bits, where X denotes the
5-6
Transceiver Reset Controller
UG-01142
2015.05.04
Altera Corporation
JESD204B IP Core Design Guidelines
Send Feedback
- JESD204B IP Core User Guide 1
- Contents 2
- Item Description 4
- Datapath Modes 8
- IP Core Variation 8
- Run-Time Configuration 9
- Channel Bonding 10
- About the JESD204B IP Core 13
- Getting Started 15
- Upgrading IP Cores 16
- IP Core Status Description 17
- Design Walkthrough 20
- Programming an FPGA Device 25
- Pin Assignments 26
- JESD204B IP Core Parameters 30
- Parameter Value Description 31
- JESD204B IP Core Testbench 35
- Configuration Preset Value 36
- Testbench Simulation Flow 37
- Subscribe 38
- Frame Clock 39
- Transmitter 41
- TX Data Link Layer 42
- Configura‐ 43
- Description 43
- MSB 6 5 4 3 2 1 LSB 43
- User Data Phase 44
- Receiver 45
- RX Data Link Layer 46
- Frame Alignment 47
- Lane Alignment 47
- ILAS Data 48
- Initial Lane Synchronization 48
- RX PHY Layer 49
- Operation 50
- Scrambler/Descrambler 51
- SYNC_N Signal 51
- Link Reinitialization 53
- Link Startup Sequence 54
- Device Clock 57
- Link Clock 58
- Local Multi-Frame Clock 59
- Clock Correlation 60
- Reset Scheme 61
- Reset Sequence 62
- Registers 80
- Access Type Definition 81
- Design Example Components 84
- PLL Reconfiguration 85
- Operation Avalon-MM 86
- Interface Signal 86
- Byte Address 86
- Offset (6bits) 86
- Bit Value 86
- Transceiver Reset Controller 87
- Pattern Generator 87
- Pattern Checker 88
- Transport Layer 89
- F Parameter f 90
- (txframe_clk frequency) f 90
- (rxframe_clk frequency) 90
- TX Path Data Remapping 100
- Altera Corporation 100
- Send Feedback 100
- UG-01142 104
- 2015.05.04 104
- F FRAMECLK_DIV TX Latency 105
- Parameter Description Value 106
- Related Information 113
- RX Path Data Remapping 114
- Serial Port Interface (SPI) 117
- Control Unit 118
- Memory Block (ROM) 119
- Finite State Machine (FSM) 120
- System Parameters 121
- Run-Time Reconfiguration 124
- System Interface Signals 125
- Signal Clock 128
- Direction Description 128
- PHY (Stratix V and Arria V) 133
- Implementation Guidelines 139
- Programmable RBD Offset 140
- Programmable LMFC Offset 143
- K K K K K RK K K K K 146
- D D D DK D D 146
- DK D DK K K 146
- Clocking Scheme 148
- JESD204B Parameters 148
- SPI Programming 149
- Additional Information 155
- Date Version Changes 156
- How to Contact Altera 157
- Contact Method Address 158
Verwandte Produkte und Handbücher für Messgeräte Altera JESD204B IP
(109 Seiten)© 2020, manymanuals.de. Alle Rechte vorbehalten. | 0.072 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Kommentare zu diesen Handbüchern