Altera JESD204B IP Bedienungsanleitung PDF herunterladen (Seite 151)

Measure the rxphy_clk or txphy_clk frequency by connecting the clock to the CLKOUT pin on the

FPGA. The frequency should be the same as link clock frequency.

Link Layer

Verify the RX PHY-link layer interface operation through these signals in the

<ip_variant_name>_inst_phy.v:

• jesd204_rx_pcs_data

• jesd204_rx_pcs_data_valid

• jesd204_rx_pcs_kchar_data

• jesd204_rx_pcs_errdetect

• jesd204_rx_pcs_disperr

Verify the RX link layer operation through these signals in the <ip_variant_name>.v:

• jesd204_rx_avs_rst_n

• rxlink_rst_n_reset_n

• rx_sysref (for Subclass 1 only)

• rx_dev_sync_n

• jesd204_rx_int

• alldev_lane_aligned

• dev_lane_aligned

• rx_somf

Use the rxlink_clk signal as the sampling clock.

Verify the TX PHY-link layer interface operation through these signals in the

<ip_variant_name>_inst_phy.v:

• jesd204_tx_pcs_data

• jesd204_rx_pcs_kchar_data

Verify the TX link layer operation through these signals in the <ip_variant_name>.v:

• jesd204_tx_avs_rst_n

• txlink_rst_n_reset_n

• tx_sysref (for Subclass 1 only)

• sync_n

• tx_dev_sync_n

• mdev_sync_n

• jesd204_tx_int

Altera recommends that you verify the JESD204B functionality by accessing the DAC SPI registers or any

debug feature provided by the DAC manufacturer.

7-4

Debugging JESD204B Link Using SignalTap II and System Console

UG-01142

2015.05.04

Altera Corporation

JESD204B IP Core Debug Guidelines

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Altera JESD204B IP Bedienungsanleitung Seite 151