Altera Internal Memory (RAM and ROM) IP Core Bedienungsanleitung PDF herunterladen (Seite 37)

Parameter Legal Values Description

Which ports should be registered?

When you select With one read port and one write

port, the following options are available:

• ‘data’, ‘wraddress’, and ‘wren’ write input ports

• ‘raddress’ and ‘rden’ read input port

• Read output port(s) ‘q’

When you select With two read/write ports, the

following options are available:

• ‘data_a’, ‘wraddress_a’, and ‘wren_a’ write input

ports

• Read output port(s) ‘q’_a and ‘q_b’

On/Off

Specifies whether to register

the read or write input and

output ports.

More Options

When you select

With one read port

and one write port,

the following options

are available:

• ‘data’ port

• ‘wraddress’ port

• ‘wren’ port

• ‘raddress’ port

• ‘q_b’ port

When you select

With two read /

write ports, the

following options are

available:

• ‘data_a’ port

• ‘data_b’ port

• ‘wraddress_a’

port

• ‘wraddress_b’

port

• ‘wren_a’ port

• ‘wren_b’ port

• ‘q_a’ port

• ‘q_b’ port

On/Off

The read and write input

ports are turned on by

default. You only need to

specify whether to register

the Q output ports.

Create one clock enable signal for each clock signal. On/Off Specifies whether to turn on

the option to create one

clock enable signal for each

clock signal.

4-12

RAM: 2-Port IP Core Parameters

UG-01068

2014.12.17

Altera Corporation

Embedded Memory Signals and Parameters

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