Altera Hybrid Memory Cube Controller Bedienungsanleitung Seite 2
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Contents
About the Altera Hybrid Memory Cube Controller IP Core.............................1-1
HMC Controller IP Core Supported Features.........................................................................................1-2
HMC Controller IP Core Supported HMC Transaction Types............................................................1-3
Device Family Support................................................................................................................................1-4
IP Core Verification.....................................................................................................................................1-4
Simulation.........................................................................................................................................1-5
Hardware Testing.............................................................................................................................1-5
Performance and Resource Utilization.....................................................................................................1-5
Device Speed Grade Support......................................................................................................................1-6
Release Information.....................................................................................................................................1-6
Getting Started with the HMC Controller IP Core............................................2-1
Installing and Licensing IP Cores..............................................................................................................2-2
OpenCore Plus IP Evaluation........................................................................................................ 2-2
Specifying IP Core Parameters and Options............................................................................................2-2
HMC Controller IP Core Parameters....................................................................................................... 2-3
RX Mapping and TX Mapping Parameters..................................................................................2-5
Files Generated for Altera IP Cores...........................................................................................................2-8
Integrating Your IP Core in Your Design................................................................................................ 2-9
Pin Constraints.................................................................................................................................2-9
Required External Blocks..............................................................................................................2-10
Simulating Altera IP Cores in other EDA Tools................................................................................... 2-16
Understanding the Testbench..................................................................................................................2-18
Generating and Running the Testbench.................................................................................................2-18
Functional Description....................................................................................... 3-1
High Level Block Diagram..........................................................................................................................3-1
Interfaces Overview.....................................................................................................................................3-2
Application Interfaces..................................................................................................................... 3-2
HMC Interface..................................................................................................................................3-2
Interface to External I
2
C Master....................................................................................................3-3
Control and Status Register Interface........................................................................................... 3-3
Status and Debug Interface.............................................................................................................3-3
Transceiver Control Interfaces.......................................................................................................3-3
Clocking and Reset Structure.....................................................................................................................3-4
Initialization..................................................................................................................................................3-5
M20K ECC Support.....................................................................................................................................3-6
Flow Control.................................................................................................................................................3-7
Error Detection and Management.............................................................................................................3-7
Testing Features........................................................................................................................................... 3-8
TOC-2
About the Altera Hybrid Memory Cube Controller IP Core
Altera Corporation
- User Guide 1
- Contents 2
- Altera Corporation 3
- Controller IP Core 4
- Device Family Support 7
- IP Core Verification 7
- Simulation 8
- Hardware Testing 8
- Device Speed Grade Support 9
- Release Information 9
- Related Information 10
- OpenCore Plus IP Evaluation 11
- UG-01152 12
- 2015.05.04 12
- Pin Constraints 18
- Required External Blocks 19
- Adding the External PLL 20
- HMC Controller IP Core 22
- Adding the External I 24
- C Master Module 24
- Quartus II 26
- Design Flow 26
- Gate-Level Simulation 26
- RTL Simulation 26
- Understanding the Testbench 27
- Functional Description 29
- Interfaces Overview 30
- Interface to External I 31
- C Master 31
- Status and Debug Interface 31
- Clocking and Reset Structure 32
- Initialization 33
- M20K ECC Support 34
- Flow Control 35
- Testing Features 36
- Application Interface Signals 38
- HMC Interface Signals 45
- Status and Debug Signals 48
- Clock and Reset Signals 49
- Code Description 53
- CONTROL Register 54
- XCVR_STATUS Register 55
- LANE_STATUS Register 55
- LINK_STATUS Register 56
- ERROR_RESPONSE Register 57
- Interrupt Related Registers 57
- Bits Field Name Type Value on 58
- Description 58
- M20K ECC Support on page 3-6 63
- Subscribe 64
- Send Feedback 64
- Arria 10 Device 65
- Switch Function Setting 66
- LED Color Meaning When Lit 66
- Additional Information 67
- Typographic Conventions 68
- Visual Cue Meaning 69
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