Altera DDR SDRAM Controller Bedienungsanleitung PDF herunterladen (Seite 55)

Chapter 3: Functional Description 3–19

Interfaces & Signals

For Stratix II devices, you have the following three options for the constraints:

■ Dedicated top and bottom I/O pins, which gives the highest performance.

■ Migratable DM, DQ, and DQS pin constraints on all sides of the device, which

allows you to migrate your design to a migration device at a later stage, and gives

less pins.

■ Non-migratable pin constraints, which give much greater flexibility and a greater

number of available pins on all sides of the device.

Interfaces & Signals

This section describes the following topics:

■ “Interface Description” on page 3–19

■ “Signals” on page 3–28

Interface Description

This section describes the following local-side interface requests:

■ “Writes” on page 3–20

■ “Reads” on page 3–21

■ “Read-Write-Read-Write” on page 3–23

■ “DDR SDRAM Initialization Timing” on page 3–25

■ “DDR2 SDRAM Initialization Timing” on page 3–26

1 These interface requests are for the native interface. For information on the

Avalon-MM interface, refer to the Avalon Interface Specifications.

The native interface is a superset of the Avalon-MM interface. The native interface has

the following additional signals. These signals, which are not part of the Avalon-MM

interface, provide extra information and control for the native interface:

■ local_rdvalid_in_n

■ local_init_done

■ local_refresh_req

■ local_refresh_ack

■ local_wdata_req

f For information on the datapath interface, refer to “Datapath” on page 3–4.

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Altera DDR SDRAM Controller Bedienungsanleitung Seite 55