Altera Cyclone V GT FPGA Bedienungsanleitung PDF herunterladen (Seite 34)

6–12 Chapter 6: Board Test System

Using the Board Test System

Cyclone V GT FPGA Development Kit September 2014 Altera Corporation

User Guide

■ Write (MBps), Read (MBps), and Total (MBps)—Show the number of bytes of

data analyzed per second.

■ DDR3x40—The theoretical maximum bandwidth is 3200 MBps.

■ DDR3x64—The theoretical maximum bandwidth is 4800 MBps.

Error Control

This group displays data errors detected during analysis and allows you to insert

errors:

■ Detected errors—Displays the number of data errors detected in the hardware.

■ Inserted errors—Displays the number of errors inserted into the transaction

stream.

■ Insert Error—Inserts a one-word error into the transaction stream each time you

click the button. Insert Error is only enabled during transaction performance

analysis.

■ Clear—Resets the Detected errors and Inserted errors counters to zeros.

Number of Addresses to Write and Read

This control allows you to determine the number of addresses for each iteration of

reads and writes.

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Altera Cyclone V GT FPGA Bedienungsanleitung Seite 34