Altera Cyclone V GT FPGA Bedienungsanleitung PDF herunterladen (Seite 28)

6–6 Chapter 6: Board Test System

Using the Board Test System

Cyclone V GT FPGA Development Kit September 2014 Altera Corporation

User Guide

■ PSS—Displays the MAX V PSS register value. Refer to Table 6–1 for the list of

available options.

■ SRST—Resets the system and reloads the FPGA with a design from flash memory

based on the other MAX V register values. Refer to Table 6–1 for more information.

1 Because the System Info tab requires that a specific design is running in the FPGA at

a specific clock speed, writing a 0 to SRST or changing the PSO value can cause the

Board Test System to stop running.

JTAG Chain

This control shows all the devices currently in the JTAG chain. The Cyclone V GT

device is always the first device in the chain. The JTAG chain is normally mastered by

the On-board USB-Blaster II.

1 If you plug in an external USB-Blaster cable to the JTAG header (J13), the On-Board

USB-Blaster II is disabled.

1 JTAG DIP switch bank (SW3) selects which interfaces are in the chain. Refer to

Table 4–1 on page 4–3 for detailed settings.

f For details on the JTAG chain, refer to the Cyclone V GT FPGA Development Board

Reference Manual. For USB-Blaster II configuration details, refer to the On-Board

USB-Blaster II page.

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Altera Cyclone V GT FPGA Bedienungsanleitung Seite 28