Altera CRC Compiler Bedienungsanleitung PDF herunterladen (Seite 23)

Chapter 3: Functional Description 3–7

Signals

Preliminary

Signals

Table 3–2 describes the I/O signals of a CRC MegaCore function.

Testbench

The testbench shows you a typical variant created by the CRC Compiler. The variant

and the testbench are fixed and may differ from the variant you create.

The testbench is available in both Verilog and VHDL, plaintext except for the CRC IP

Functional Simulation models. The testbench models are synthesizable RTL which

allows you to compile and to run the testbench in hardware. The architecture is

shown in Figure 3–11.

Table 3–2. CRC Signals

Signal Direction Description

clk In System clock.

reset_n In Asynchronous reset signal, which is active at 0.

data[(n-1):0] In Message bits for generator; codeword bits for checker, where n is a power of 2,

from 1 through 256, (1, 2, 4, 8,16, 32, 64,128, or 256).

datavalid In Asserted by the source to indicate new packet data.

startofpacket In Asserted by the source to mark the beginning of a packet. This signal is present

only when the parameter Optimize for: speed is set to ON or Number of leading

bits to ignore in First word is greater than 0.

endofpacket In Asserted by the source to mark the end of a packet.

empty[(n-1):0] In The number of empty symbols during cycles that contain the end of a packet.

This signal must be set to 0 during other cycles when datavalid is

asserted. The value of n equals log

(number of symbols per word). This signal

is present only when the parameter Symbols per word is greater than 1.

checksum[(n-1):0] Out Computed CRC output, where n equals the order of the generator polynomial.

This signal is present only in CRC generator.

crcbad Out Asserted if the previous packet had an incorrect CRC. This signal is present only

in CRC checker.

crcvalid Out Asserted when the core has completed calculation of the checksum or

crcbad value.

Multi-Channel Signals

datachannel[(n-1):0] In The channel on which data is received by the generator or checker. The value of

n equals log

(number of CRC channels).

chaninitdone Out Asserted when the MegaCore function has completed its internal initialization

process and ready to receive data for processing. User applications must wait

for chaninitdone to be asserted before sending data to the MegaCore

function for processing. The MegaCore function reinitializes itself each time the

reset_n signal is asserted.

crcchannel[(n-1):0] Out Indicates the channel whose result is presented at the checksum (generator)

or crcbad (checker) output signal. The value of n equals log

(number of CRC

channels).

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 29 30

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