Altera Clock Control Block IP Core Bedienungsanleitung PDF herunterladen (Seite 19)

Chapter 3: Functional Description 3–7

ALTCLKCTRL Megafunction Ports

February 2014 Altera Corporation Clock Control Block (ALTCLKCTRL) Megafunction

User Guide

ALTCLKCTRL Megafunction Ports

Table 3–3 and Table 3–4 lists the input and output ports for the ALTCLKCTRL

megafunction.

Input Ports

Output Ports

Table 3–3. ALTCLKCTRL Megafunction Input Ports

Port Name Required Description Comments

clkselect[]

Input that dynamically selects

the clock source to drive the

clock network that is driven by

the clock buffer.

Input port

[1 DOWNTO 0]

wide.

If omitted, the default is GND.

If this signal is connected, only the global clock

network can be driven by this clock control block.

ena

No Clock enable of the clock buffer

If omitted, the default value is V

This option cannot be used for periphery clock

network path in Stratix

III and Stratix IV devices.

inclk[]

Yes Clock input of the clock buffer

Input port

[3 DOWNTO 0]

wide.

You can specify up to four clock inputs,

inclk[3:0]

Clock pins, clock outputs from the PLL, and core

signals can drive the

inclk[]

port.

Multiple clock inputs are only supported for the global

and auto-selected clock networks.

Binary Value Signal Selection

00 inclk[0]

01 inclk[1]

10 inclk[2]

11 inclk[3]

Table 3–4. ALTCLKCTRL Megafunction Output Ports

Port Name Required Description Comments

outclk

Yes Output of the clock buffer. —

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 25 26

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