Altera Arria V GX FPGA Development Board Bedienungsanleitung PDF herunterladen (Seite 76)

2–66 Chapter 2: Board Components

Memory

Arria V GX FPGA Development Board November 2013 Altera Corporation

Reference Manual

DDR3B_A10

C32 1.5-V SSTL Class I Address bus

DDR3B_A11

D32 1.5-V SSTL Class I Address bus

DDR3B_A12

N31 1.5-V SSTL Class I Address bus

DDR3B_A13

P31 1.5-V SSTL Class I Address bus

DDR3B_BA0

M32 1.5-V SSTL Class I Bank address bus

DDR3B_BA1

N32 1.5-V SSTL Class I Bank address bus

DDR3B_BA2

J34 1.5-V SSTL Class I Bank address bus

DDR3B_CASN

L33 1.5-V SSTL Class I Row address select

DDR3B_CKE

E31 1.5-V SSTL Class I Column address select

DDR3B_CLK_N

C30 1.5-V SSTL Class I Differential output clock

DDR3B_CLK_P

B30 1.5-V SSTL Class I Differential output clock

DDR3B_CSN

L34 1.5-V SSTL Class I Chip select

DDR3B_ODT

L31 1.5-V SSTL Class I On-die termination enable

DDR3B_RASN

K34 1.5-V SSTL Class I Row address select

DDR3B_RESETN

G30 1.5-V SSTL Class I Reset

DDR3B_WEN

M33 1.5-V SSTL Class I Write enable

DDR3C (U19)

DDR3C_DM0

M21 1.5-V SSTL Class I Write mask byte lane

DDR3C_DM1

B22 1.5-V SSTL Class I Write mask byte lane

DDR3C_DQ0

D20 1.5-V SSTL Class I Data bus byte lane

DDR3C_DQ1

H21 1.5-V SSTL Class I Data bus byte lane

DDR3C_DQ2

D21 1.5-V SSTL Class I Data bus byte lane

DDR3C_DQ3

J21 1.5-V SSTL Class I Data bus byte lane

DDR3C_DQ4

A21 1.5-V SSTL Class I Data bus byte lane

DDR3C_DQ5

G21 1.5-V SSTL Class I Data bus byte lane

DDR3C_DQ6

A22 1.5-V SSTL Class I Data bus byte lane

DDR3C_DQ7

C20 1.5-V SSTL Class I Data bus byte lane

DDR3C_DQ8

A23 1.5-V SSTL Class I Data bus byte lane

DDR3C_DQ9

E22 1.5-V SSTL Class I Data bus byte lane

DDR3C_DQ10

L22 1.5-V SSTL Class I Data bus byte lane

DDR3C_DQ11

C22 1.5-V SSTL Class I Data bus byte lane

DDR3C_DQ12

N22 1.5-V SSTL Class I Data bus byte lane

DDR3C_DQ13

F22 1.5-V SSTL Class I Data bus byte lane

DDR3C_DQ14

P22 1.5-V SSTL Class I Data bus byte lane

DDR3C_DQ15

J22 1.5-V SSTL Class I Data bus byte lane

DDR3C_DQS_N0

B21 1.5-V SSTL Class I Data strobe N byte lane

DDR3C_DQS_N1

D23 1.5-V SSTL Class I Data strobe N byte lane

DDR3C_DQS_P0

A20 1.5-V SSTL Class I Data strobe P byte lane

DDR3C_DQS_P1

C23 1.5-V SSTL Class I Data strobe P byte lane

Table 2–56. DDR3 x64 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)

Board Reference

Schematic

Signal Name

Arria V GX FPGA

Pin Number

I/O Standard Description

1 2 ... 71 72 73 74 75 76 77 78 79 80 81 ... 89 90

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