Altera Arria V GX FPGA Development Board Bedienungsanleitung Seite 73

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Seitenansicht 72
Chapter 2: Board Components 2–63
Memory
November 2013 Altera Corporation Arria V GX FPGA Development Board
Reference Manual
DDR3B/C for FPGA 2
The development board supports a 16Mx64x8 bank DDR3 SDRAM interface on
FPGA 2 for very high-speed sequential memory access. The 64-bit data bus consists of
four x16 devices with a single address or command bus. This interface connects to the
vertical I/O banks on the top edge of the FPGA.
This DDR3 SDRAM has two interface options. The first option is a x32 interface using
a memory hard controller. The second option is a x64 interface using a memory soft
controller.
Table 255 lists the DDR3B (x32 hard controller) pin assignments, signal names, and
functions. The signal names and types are relative to the Arria V GX FPGA in terms of
I/O setting and direction.
C2
DDR3A_DQ11
H31 1.5-V SSTL Class I Data bus byte lane
A7
DDR3A_DQ12
B31 1.5-V SSTL Class I Data bus byte lane
A2
DDR3A_DQ13
E31 1.5-V SSTL Class I Data bus byte lane
B8
DDR3A_DQ14
A31 1.5-V SSTL Class I Data bus byte lane
A3
DDR3A_DQ15
C31 1.5-V SSTL Class I Data bus byte lane
G3
DDR3A_DQS_N0
M33 1.5-V SSTL Class I Data strobe N byte lane
B7
DDR3A_DQS_N1
B33 1.5-V SSTL Class I Data strobe N byte lane
F3
DDR3A_DQS_P0
L33 1.5-V SSTL Class I Data strobe P byte lane
C7
DDR3A_DQS_P1
N30 1.5-V SSTL Class I Data strobe P byte lane
L8
DDR3A_ZQ01
1.5-V SSTL Class I ZQ impedance calibration
Table 2–54. DDR3A Devices Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5)
Board Reference
Schematic
Signal Name
Arria V GX FPGA
Pin Number
I/O Standard Description
Table 2–55. DDR3 x32 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)
Board Reference
Schematic
Signal Name
Arria V GX FPGA
Pin Number
I/O Standard Description
DDR3B (U6, U12)
N3
DDR3B_A0
B31 1.5-V SSTL Class I Address bus
P7
DDR3B_A1
A30 1.5-V SSTL Class I Address bus
P3
DDR3B_A2
A31 1.5-V SSTL Class I Address bus
N2
DDR3B_A3
A32 1.5-V SSTL Class I Address bus
P8
DDR3B_A4
A33 1.5-V SSTL Class I Address bus
P2
DDR3B_A5
B33 1.5-V SSTL Class I Address bus
R8
DDR3B_A6
H31 1.5-V SSTL Class I Address bus
R2
DDR3B_A7
J31 1.5-V SSTL Class I Address bus
T8
DDR3B_A8
C31 1.5-V SSTL Class I Address bus
R3
DDR3B_A9
D31 1.5-V SSTL Class I Address bus
L7
DDR3B_A10
C32 1.5-V SSTL Class I Address bus
R7
DDR3B_A11
D32 1.5-V SSTL Class I Address bus
N7
DDR3B_A12
N31 1.5-V SSTL Class I Address bus
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