Altera Arria V GX FPGA Development Board Bedienungsanleitung PDF herunterladen (Seite 69)

Chapter 2: Board Components 2–59

Memory

November 2013 Altera Corporation Arria V GX FPGA Development Board

Reference Manual

Table 2–54 lists the DDR3A (x72 soft controller) pin assignments, signal names, and

functions. The signal names and types are relative to the Arria V GX FPGA in terms of

I/O setting and direction.

Table 2–54. DDR3A Devices Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 5)

Board Reference

Schematic

Signal Name

Arria V GX FPGA

Pin Number

I/O Standard Description

DDR3A (U11, U18, U21, U28)

DDR3A_A0

M34 1.5-V SSTL Class I Address bus

DDR3A_A1

H25 1.5-V SSTL Class I Address bus

DDR3A_A2

F32 1.5-V SSTL Class I Address bus

DDR3A_A3

P28 1.5-V SSTL Class I Address bus

DDR3A_A4

L24 1.5-V SSTL Class I Address bus

DDR3A_A5

G32 1.5-V SSTL Class I Address bus

DDR3A_A6

R21 1.5-V SSTL Class I Address bus

DDR3A_A7

K30 1.5-V SSTL Class I Address bus

DDR3A_A8

D21 1.5-V SSTL Class I Address bus

DDR3A_A9

M30 1.5-V SSTL Class I Address bus

DDR3A_A10

J28 1.5-V SSTL Class I Address bus

DDR3A_A11

M21 1.5-V SSTL Class I Address bus

DDR3A_A12

G28 1.5-V SSTL Class I Address bus

DDR3A_A13

M31 1.5-V SSTL Class I Address bus

DDR3A_BA0

G30 1.5-V SSTL Class I Bank address bus

DDR3A_BA1

T24 1.5-V SSTL Class I Bank address bus

DDR3A_BA2

K34 1.5-V SSTL Class I Bank address bus

DDR3A_CASN

D32 1.5-V SSTL Class I Row address select

DDR3A_CKE

K29 1.5-V SSTL Class I Column address select

DDR3A_CLK_N

F34 1.5-V SSTL Class I Differential output clock

DDR3A_CLK_P

E34 1.5-V SSTL Class I Differential output clock

DDR3A_CSN

F31 1.5-V SSTL Class I Chip select

DDR3A_ODT

E33 1.5-V SSTL Class I On-die termination enable

DDR3A_RASN

A32 1.5-V SSTL Class I Row address select

DDR3A_RESETN

J31 1.5-V SSTL Class I Reset

DDR3A_WEN

G29 1.5-V SSTL Class I Write enable

DDR3A (U7)