Altera Arria V Avalon-MM Bedienungsanleitung Seite 51
- Seite / 166
- Inhaltsverzeichnis
- LESEZEICHEN
Bewertet. / 5. Basierend auf Kundenbewertungen
Configuration Space Register Access
The tl_cfg_ctl signal is a multiplexed bus that contains the contents of Configuration Space registers as
shown in the figure below. Information stored in the Configuration Space is accessed in round robin
order where tl_cfg_add indicates which register is being accessed. The following table shows the layout
of configuration information that is multiplexed on tl_cfg_ctl.
Figure 4-6: Multiplexed Configuration Register Information Available on tl_cfg_ctl
Fields in blue are available only for Root Ports.
0
1
cfg_dev_ctrl[15:0]
31
24
23
16
15
8
7
0
2
3
4
5
6
7
8
9
A
B
C
D
E
F
cfg_dev_ctrl2[15:0]
cfg_link_ctrl[15:0] cfg_link_ctrl2[15:0]
cfg_dev_ctrl[14:12] =
Max Read Req Size
16’h0000 cfg_slot_ctrl[15:0]
8’h00 cfg_root_ctrl[7:0]
cfg_secbus[7:0] cfg_subbus[7:0]cfg_sec_ctrl[15:0]
cfg_msi_addr[11:0] cfg_io_bas[19:0]
cfg_dev_ctrl[7:5] =
Max Payload
cfg_pgm_cmd[15:0]
cfg_msi_addr[43:32] cfg_io_lim[19:0]
8’h00 cfg_np_bas[11:0] cfg_np_lim[11:0]
cfg_msi_addr[31:12] cfg_pr_bas[43:32]
cfg_pr_bas[31:0]
cfg_msi_addr[63:44] cfg_pr_lim[43:32]
cfg_pr_lim[31:0]
cfg_msixcsr[15:09] cfg_msicsr[15:0]
cfg_pmcsr[31:0]
6’h00, tx_ecrcgen[25],
rx_ecrccheck[24]
cfg_tcvcmap[23:0]
cfg_msi_data[15:0] 3’b00 0
cfg_busdev[12:0]
Table 4-12: Configuration Space Register Descriptions
Register Width Direction Description
cfg_dev_ctrl_func<n>
16 Output
cfg_dev_ctrl_func<n>[15:0] is Device Control
register for the PCI Express capability structure.
cfg_dev_ctrl2
16 Output cfg_dev2ctrl[15:0] is Device Control 2 for the
PCI Express capability structure.
UG-01105_avmm
2014.12.15
Configuration Space Register Access
4-21
Interfaces and Signal Descriptions
Altera Corporation
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Release Information 6
- Device Family Support 6
- Altera FPGA 7
- IP Core Verification 9
- Debug Features 9
- Recommended Speed Grades 10
- Hard IP for PCI Express 12
- Running Qsys 13
- Generating the Example Design 14
- Programming a Device 18
- Quartus II Programmer 19
- Parameter Settings 20
- Parameter Value Description 21
- Device Capabilities 23
- Error Reporting 24
- Link Capabilities 25
- MSI and MSI-X Capabilities 25
- Power Management 27
- Subscribe 31
- RX Avalon-MM Master Signals 33
- Clock Signals 38
- Reset Signals 38
- Signal Direction Description 39
- Hard IP Status 40
- IntxReq_i 44
- IntAck_o 44
- Hard IP Status Extension 46
- Field and Bit Map 54
- 0134678951 54
- Serial Interface Signals 55
- 9 Ch 18 Ch 56
- Variant Data CMU Clock 57
- PIPE Interface Signals 58
- Test Signals 62
- Registers 63
- Altera-Defined VSEC Registers 71
- CvP Registers 72
- Address Range Register 76
- Bit Name Access Description 77
- Bits Name Access Description 78
- PCI Express Mailbox Registers 79
- Avalon-MM Mailbox Registers 83
- Address Name Access 84
- Description 84
- Byte Offset 84
- Register Dir Description 84
- Sending a Write TLP 90
- Root Port TLP Data Registers 92
- Bits Register Description 95
- Reset and Clocks 98
- Example Design 99
- UG-01105_avmm 100
- 2014.12.15 100
- Clock Domains 102
- Data Rate Frequency 103
- Related Information 103
- Clock Summary 104
- Interrupts for Endpoints 105
- MSI/MSI‑X Support 107
- Qsys System 108
- Error Handling 109
- Physical Layer Errors 110
- Data Link Layer Errors 110
- Transaction Layer Errors 111
- Error Type Description 112
- Status Bit Conditions 115
- IP Core Architecture 117
- Hard IP for PCI Express 118
- Clocks and Reset 119
- Transceiver Reconfiguration 119
- Interrupts 119
- Data Link Layer 120
- Altera Corporation 121
- Send Feedback 121
- Physical Layer 122
- TX Packets 123
- Avalon‑MM Bridge TLPs 127
- Byte Enable Value Description 128
- PCI Express Avalon-MM Bridge 130
- RX Block 136
- Avalon-MM RX Master Block 136
- TX Block 137
- Interrupt Handler Block 137
- Design Implementation 139
- Making Pin Assignments 140
- Optional Features 141
- ECRC on the RX Path 142
- ECRC on the TX Path 143
- Enable PLL calibration 145
- Debugging 148
- Setting Up Simulation 149
- Use Third-Party PCIe Analyzer 150
- BIOS Enumeration Issues 151
- Address[31:2] 152
- Figure A-6: I/O Read Request 154
- 7 6 5 4 3 2 1 0 158
- Core Config 8 4 1 158
- Additional Information 160
- Date Version Changes Made 161
- How to Contact Altera 163
- Typographic Conventions 164
- Visual Cue Meaning 165
Verwandte Produkte und Handbücher für Messgeräte Altera Arria V Avalon-MM
Messgeräte Altera DDR3 SDRAM High-Performance Controller and ALTMEMP Bedienungsanleitung
(10 Seiten)
(10 Seiten)
Messgeräte Altera DDR SDRAM High-Performance Controllers and ALTMEMP Bedienungsanleitung
(140 Seiten)
(140 Seiten)
Messgeräte Altera Floating-Point Bedienungsanleitung
(157 Seiten)
(157 Seiten)
Messgeräte Altera JESD204B IP Bedienungsanleitung
(158 Seiten)
(158 Seiten)
© 2020, manymanuals.de. Alle Rechte vorbehalten. | 0.056 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Kommentare zu diesen Handbüchern