Altera Arria II GX FPGA Development Board Bedienungsanleitung PDF herunterladen (Seite 30)

2–22 Chapter 2: Board Components

Clock Circuitry

Arria II GX FPGA Development Board Reference Manual February 2011 Altera Corporation

SMA or

100.000 MHz

(Default

Frequency) (1)

CLKIN_BOT_P

AJ19

LVDS

Input to the fan-out buffer (U33) which drives

LVDS input to the bottom edge of PLL input.

CLKIN_BOT_N

AK19

CLKIN_REF_Q2_P U29 Input to the fan-out buffer (U33) which drives

LVDS input to the transceiver Q2 reference

clock input with 100  OCT.

CLKIN_REF_Q2_N U30

125.000 MHz

(Default

Frequency) (2)

CLKIN_TOP_P

F18

LVDS

Programmable oscillator which drives LVDS

input to the top edge of PLL input.

CLKIN_TOP_N

F17

CLK_REF_Q1_1_P AA29

Programmable oscillator which drives LVDS

input to the transceiver Q1 reference clock

input with 100  OCT.

CLK_REF_Q1_1_N AA30

CLK_REF_Q1_2_P W29

CLK_REF_Q1_2_N W30

CLK_REF_Q3_P (3) N29 Programmable oscillator which drives LVDS

input to the transceiver Q3 reference clock

input with 100  OCT.

CLK_REF_Q3_N (3) N30

Samtec HSMC

HSMA_CLKIN0

AP17 LVTTL

Single-ended input from the installed HSMC

port A cable or board.

Samtec HSMC

HSMA_CLKIN_P1

LVDS or LVTTL

LVDS input from the installed HSMC port A

cable or board. Can also support two LVTTL

inputs.

HSMA_CLKIN_N1

Samtec HSMC

HSMA_CLKIN_P2

K18

LVDS or LVTTL

LVDS input from the installed HSMC port A

cable or board. Can also support two LVTTL

inputs.

HSMA_CLKIN_N2

J18

Samtec HSMC

HSMB_CLKIN0 (4)

AP16 LVTTL

Single-ended input from the installed HSMC

port B cable or board.

PCI Express

Edge

PCIE_REFCLK_P

AE29

HCSL

High-Speed Current Steering Logic (HCSL)

input from the PCI Express edge connector.

PCIE_REFCLK_N

AE30

Notes to Table 2–20:

(1) CDCM61001 has a default frequency of 100 MHz, but can also be set by the MAX II CPLD to frequencies of 125 MHz and 156.25 MHz.

(2) CDCM61004 has a default frequency of 125 MHz, but can also be set by the MAX II CPLD to frequencies of 100 MHz and 156.25 MHz.

(3) Transceiver Q3 is only available when the Arria II GX FPGA development board is populated with the EP2AGX260 device.

(4) HSMB is only available when the Arria II GX FPGA development board is populated with the EP2AGX260 device.

Table 2–20. Arria II GX FPGA Development Board Clock Inputs (Part 2 of 2)

Source Schematic Signal Name Pin I/O Standard Description

1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 63 64

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