Altera Arria 10 Avalon-ST Bedienungsanleitung Seite 203
- Seite / 275
- Inhaltsverzeichnis
- LESEZEICHEN
Bewertet. / 5. Basierend auf Kundenbewertungen
The top-level of the testbench instantiates four main modules:
• <qsys_systemname>— This is the example Endpoint design. For more information about this module,
refer to Chaining DMA Design Examples.
• altpcietb_bfm_top_rp.v—This is the Root Port PCI Express BFM. For more information about this
module, refer to Root Port BFM.
• altpcietb_pipe_phy—There are eight instances of this module, one per lane. These modules intercon‐
nect the PIPE MAC layer interfaces of the Root Port and the Endpoint. The module mimics the
behavior of the PIPE PHY layer to both MAC interfaces.
• altpcietb_bfm_driver_chaining—This module drives transactions to the Root Port BFM. This is the
module that you modify to vary the transactions sent to the example Endpoint design or your own
design. For more information about this module, refer to Root Port Design Example.
In addition, the testbench has routines that perform the following tasks:
• Generates the reference clock for the Endpoint at the required frequency.
• Provides a PCI Express reset at start up.
Note: Before running the testbench, you should set the following parameters in <instantiation_name>_tb/
sim/<instantiation_name>_tb.v:
• serial_sim_hwtcl: Set to 1 for serial simulation and 0 for PIPE simulation.
• enable_pipe32_sim_hwtcl: Set to 0 for serial simulation and 1 for PIPE simulation.
Related Information
• Getting Started with the Arria 10 Hard IP for PCI Express on page 2-1
• Chaining DMA Design Examples on page 17-4
• Root Port Testbench on page 17-3
• Root Port Design Example on page 17-20
Root Port Testbench
This testbench simulates up to an ×8 PCI Express link using either the PIPE interfaces of the Root Port
and Endpoints or the serial PCI Express interface. The testbench design does not allow more than one
PCI Express link to be simulated at a time. The top-level of the testbench instantiates four main modules:
• <qsys_systemname>— Name of Root Port This is the example Root Port design. For more information
about this module, refer to Root Port Design Example.
• altpcietb_bfm_ep_example_chaining_pipen1b—This is the Endpoint PCI Express mode described in
the section Chaining DMA Design Examples.
• altpcietb_pipe_phy—There are eight instances of this module, one per lane. These modules connect
the PIPE MAC layer interfaces of the Root Port and the Endpoint. The module mimics the behavior of
the PIPE PHY layer to both MAC interfaces.
• altpcietb_bfm_driver_rp—This module drives transactions to the Root Port BFM. This is the module
that you modify to vary the transactions sent to the example Endpoint design or your own design. For
more information about this module, see Test Driver Module.
UG-01145_avst
2015.05.04
Root Port Testbench
17-3
Testbench and Design Example
Altera Corporation
Send Feedback
- Solutions 1
- Contents 2
- Datasheet 8
- Arria 10 Features 9
- Interface 10
- UG-01145_avst 11
- 2015.05.04 11
- Release Information 13
- Device Family Support 14
- Configurations 14
- Altera FPGA 15
- Debug Features 17
- IP Core Verification 18
- Recommended Speed Grades 18
- Qsys Design Flow 21
- Generating the Testbench 22
- Simulating the Example Design 22
- Directory Description 23
- Time TLP Type Payload 23
- TLP Header 23
- Modifying the Example Design 26
- Component 27
- File Name Description 28
- Subscribe 31
- 2014.08.18 32
- Generating the Qsys System 33
- Parameter Value 34
- Parameter Settings 44
- Parameter Value Description 45
- Device Capabilities 52
- Error Reporting 53
- Link Capabilities 54
- MSI and MSI-X Capabilities 55
- Slot Capabilities 56
- Power Management 57
- PHY Characteristics 58
- Avalon‑ST RX Interface 68
- Packet TLP 73
- Aligned Addresses 77
- Avalon-ST TX Interface 82
- Single Packet Per Cycle 95
- Data 0 Header 2 96
- Clock Signals 97
- Signal Direction Description 100
- Related Information 101
- ECRC Forwarding 102
- Error Signals 102
- Interrupts for Endpoints 103
- Interrupts for Root Ports 104
- Completion Side Band Signals 104
- Signal Directi 105
- Description 105
- Parity Signals 107
- LMI Signals 108
- Altera Corporation 112
- Send Feedback 112
- D E F 0 1 2 3 113
- Field and Bit Map 117
- 0134678951 117
- Bit(s) Field Description 118
- Power Management Signals 120
- 15 011623 8 2791213142431 121
- Bits Field Description 122
- Serial Data Signals 123
- PIPE Interface Signals 123
- Test Signals 128
- Registers 129
- Altera-Defined VSEC Registers 136
- CvP Registers 137
- Bits Register Description 141
- Arria 10 Reset and Clocks 144
- Clock Domains 147
- Clock Summary 149
- Interrupts 150
- MSI Interrupts 151
- Allocated 152
- Implementing MSI-X Interrupts 153
- Legacy Interrupts 155
- Error Handling 157
- Physical Layer Errors 158
- Data Link Layer Errors 158
- Transaction Layer Errors 159
- Error Type Description 160
- Status Bit Conditions 163
- IP Core Architecture 165
- Hard IP for PCI Express 166
- Top-Level Interfaces 167
- Clocks and Reset 168
- Hard IP Reconfiguration 168
- Transaction Layer 169
- Configuration Space 170
- (Soft Logic) 172
- Data Link Layer 174
- Physical Layer 176
- TX Packets 177
- Supported Message Types 179
- Power Management Messages 180
- Error Signaling Messages 181
- Locked Transaction Message 182
- Slot Power Limit Message 182
- Vendor-Defined Messages 182
- Hot Plug Messages 183
- Receive Buffer Reordering 185
- Using Relaxed Ordering 187
- Throughput Optimization 190
- Throughput of Posted Writes 192
- Design Implementation 194
- SDC Timing Constraints 195
- Optional Features 196
- ECRC on the RX Path 197
- ECRC on the TX Path 198
- TLP on Applica‐ 199
- TLP on Link Comments 199
- Testbench and Design Example 201
- Root Port Testbench 203
- Chaining DMA Design Examples 204
- Root Complex 205
- Chaining DMA 205
- Hard IP for 205
- PCI Express 205
- BAR/Address Map 208
- Memory BAR Mapping 209
- Bit Field Description 210
- Addr Register Name 211
- Byte Address 213
- Offset to Base 213
- Descriptor Type Description 213
- Test Driver Module 215
- DMA Write Cycles 216
- DMA Read Cycles 218
- Root Port Design Example 220
- Root Port 221
- Variation 221
- (variation_name.v) 221
- Root Port BFM 222
- BFM Configuration Procedures 223
- BFM Request Interface 223
- BFM Memory Map 224
- Offset (Bytes) Description 226
- BFM Procedures and Functions 230
- Location altpcietb_bfm_rdwr.v 231
- Shared Memory Constants 239
- Constant Description 240
- Location 245
- Setting Up Simulation 257
- Debugging 259
- Use Third-Party PCIe Analyzer 263
- BIOS Enumeration Issues 263
- Frequently Asked Questions 264
- 7 6 5 4 3 2 1 0 265
- Core Config 8 4 1 265
- Additional Information 267
- Date Version Changes Made 268
- How to Contact Altera 272
- Typographic Conventions 273
- Visual Cue Meaning 274
Verwandte Produkte und Handbücher für Messgeräte Altera Arria 10 Avalon-ST
Messgeräte Altera DDR SDRAM High-Performance Controllers and ALTMEMP Bedienungsanleitung
(140 Seiten)
(140 Seiten)
Messgeräte Altera Floating-Point Bedienungsanleitung
(157 Seiten)
(157 Seiten)
Messgeräte Altera JESD204B IP Bedienungsanleitung
(158 Seiten)
(158 Seiten)
Messgeräte Altera Nios II Embedded Evaluation Kit Cyclone III Editio Bedienungsanleitung
(80 Seiten)
(80 Seiten)
Messgeräte Altera SCFIFO Bedienungsanleitung
(28 Seiten)
(28 Seiten)
© 2020, manymanuals.de. Alle Rechte vorbehalten. | 0.091 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Kommentare zu diesen Handbüchern