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Table 11-5: ALTFP_INV_SQRT IP Core Input Signals

Port Name Required Description

aclr No Asynchronous clear. When the aclr port is asserted high, the

function is asynchronously cleared.

clk_en No Clock enable. When the clk_en port is asserted high, an

inversion value operation takes place. When signal is asserted

low, no operation occurs and the outputs remain unchanged.

clock Yes Clock input to the megafunction.

data[] Yes Floating-point input data. The MSB is the sign bit, the next

MSBs are the exponent, and the LSBs are the mantissa. This

input port size is the total width of the sign bit, exponent bits,

and mantissa bits.

Table 11-6: ALTFP_INV_SQRT IP Core Output Signals

Port Name Required Description

result[] Yes The floating-point inverse result of the value at the data[]

input port. The MSB is the sign bit, the next MSBs are the

exponent, and the LSBs are the mantissa. The size of this port is

the total width of the sign bit, exponent bits, and mantissa bits.

zero No Zero exception output. Asserted when the value at the

result[] port is a zero.

division_by_zero No Division-by-zero exception output. Asserted when the

denominator input is a zero.

nan No NaN exception output. Asserted when an invalid inversion of

square root occurs, such as the square root of a negative

number. In this case, a NaN value is output to the result[]

output port. Any operation involving a NaN will also produce a

NaN.

Parameters

UG-01058

2014.12.19

Parameters

11-5

ALTFP_INV_SQRT IP Core

Altera Corporation

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Altera Floating-Point Bedienungsanleitung Seite 91