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This design example implements a floating-point multiplier for the multiplication of double-precision
format numbers. All the optional input ports (clk_en and aclr) and output ports (overflow, underflow,
zero, and nan) are enabled.
In this example, the latency is set to 6 clock cycles. Therefore, every multiplication result appears at the
result port 6 clock cycles later.
Table 7-4: Summary of Input Values and Corresponding Outputs
This table lists the inputs and corresponding outputs obtained from the simulation in the waveform.
Time Event
0 ns, start-up dataa[] value: 0000 0000 0000 0000h
datab[] value: 4037 742C 3C9E ECC0h
Output value: All values seen on the output port before the 6th clock cycle are
merely due to the behavior of the system during start-up and should be disregarded.
110 ns Output value: 0000 0000 0000 0000h
Exception handling ports: zero asserts
The multiplication of zero at the input port dataa[], and a non-zero value at the
input port datab[] results in a zero.
600 ns dataa[] value: 7FF0 0000 0000 0000h
datab[] value: 4037 742C 3C9E ECC0h
This is the multiplication of an infinity value and a normal value.
710 ns Output value: 7FF0 0000 0000 0000h
Exception handling ports: overflow asserts
The multiplication of an infinity value and a normal value results in infinity. All
multiplications with an infinity value results in infinity except when infinity is
multiplied with a zero.
Parameters
7-4
Parameters
UG-01058
2014.12.19
Altera Corporation
ALTFP_MULT IP Core
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About Floating-Point IP Cores 7
- Design Flow 8
- Using the Parameter Editor 10
- File Name Description 12
- Upgrading IP Cores 15
- Related Information 18
- Floating-Point Formats 19
- Special Case Numbers 20
- Non-IEEE-754 Standard Format 21
- Integer bits 22
- Fraction bits 22
- VHDL Component Declaration 24
- VHDL LIBRARY-USE Declaration 24
- ALTERA_FP_MATRIX_INV IP Core 25
- Triangular Matrix Inversion 29
- Matrix Multiplication 29
- Matrix Inversion Operation 29
- Precision Format Numbers 30
- Sample Matrix Data 32
- Matrix Data 33
- ALTERA_FP_MATRIX_INV Signals 34
- ALTERA_FP_MATRIX_MULT IP Core 36
- . . . N-10 . . 38
- . . . N-10 38
- ALTERA_FP_MATRIX_MULT 39
- Parameter Value Description 40
- ALTERA_FP_ACC_CUSTOM IP Core 42
- ALTERA_FP_ACC_CUSTOM Signals 44
- ALTFP_ADD_SUB IP Core 48
- ALTFP_ADD_SUB Signals 51
- ALTFP_ADD_SUB 52
- ALTFP_ADD_SUB Parameters 53
- ALTFP_DIV IP Core 55
- ALTFP_DIV Truth Table 56
- ALTFP_DIV Signals 60
- ALTFP_DIV Parameters 61
- ALTFP_MULT IP Core 63
- Parameters 66
- ALTFP_MULT Signals 67
- ALTFP_SQRT 69
- ALTFP_SQRT Truth Table 70
- ALTFP_SQRT Signals 72
- ALTFP_SQRT Parameters 74
- ALTFP_EXP IP Core 75
- ALTFP_EXP Signals 78
- ALTFP_EXP 79
- ALTFP_EXP Parameters 80
- ALTFP_INV IP Core 81
- ALTFP_INV_SQRT IP Core 87
- ALTFP_INV_SQRT 90
- ALTFP_LOG 93
- ALTFP_ATAN IP Core 99
- ALTFP_ATAN Parameters 100
- Parameter 101
- Type Required Description 101
- ALTFP_SINCOS IP Core 102
- ALTFP_SINCOS Signals 103
- ALTFP_SINCOS Parameters 104
- ALTFP_ABS IP Core 105
- UG-01058 106
- 2014.12.19 106
- ALTFP_ABS Signals 107
- ALTFP_ABS 108
- ALTFP_ABS Parameters 109
- ALTFP_COMPARE IP Core 111
- Format Numbers 112
- ALTFP_COMPARE Signals 113
- ALTFP_COMPARE Parameters 114
- ALTFP_CONVERT IP Core 116
- ALTFP_CONVERT Output Latency 117
- Point Format Numbers 121
- Time Event 122
- ALTFP_CONVERT Signals 123
- ALTFP_CONVERT Parameters 125
- ALTERA_FP_FUNCTIONS IP Core 128
- Function Description 129
- ALTERA_FP_FUNCTIONS Signals 151
- Altera Corporation 152
- Send Feedback 152
- Document Revision History 156
- Date Document 157
- Changes Made 157
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