Altera Floating-Point Bedienungsanleitung Seite 39
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The following lists the key features of the architecture:
• Matrix A and B storage are double buffered to allow processing to happen in parallel with data loading.
• Where the number of columns of A (A_COLUMNS) and rows of B (same as A_COLUMNS) are greater than
the size of the dot product (VECTOR_SIZE), the rows of A and columns of B are divided into sub rows
and sub columns respectively, each containing VECTOR_SIZE elements. In this case, A_COLUMNS/
VECTOR_SIZE iterations are needed to compute a full dot product corresponding to a single output
element.
• Matrix B memory has sufficient bandwidth so that all the data needed for the dot product can be
loaded at once.
• Matrix A memory is allocated with less bandwidth. The bandwidth of the matrix A is a parameter
(NUM_BLOCKS) that you can control. A sub row of matrix A is loaded into local registers over a number
of cycles before an iteration of the dot product. Once a sub row of Matrix A has been loaded into local
registers, all partial dot products involving that sub row are computed before another sub row is
loaded.
• For Arria 10 devices, where hardened single precision floating-point DSP blocks exist, those will be
used for single precision floating point arithmetic.
The matrix multiply architecture is not optimized for sparse matrices and constant matrices.
ALTERA_FP_MATRIX_MULT Signals
Figure 3-4: ALTERA_FP_MATRIX_MULT Signals
This figure shows the signals for the ALTERA_FP_MATRIX_MULT IP core.
clk
reset_n
a_ready
a_valid
a_data
inst
ALTERA_FP_MATRIX_MULT
c_valid
c_ready
c_data
b_ready
b_valid
b_data
These tables list the signals for the ALTERA_FP_MATRIX_MULT IP core.
Table 3-2: ALTERA_FP_MATRIX_MULT Input Signals
Port Name Required Description
clk Yes The clock input port for the IP core.
3-4
ALTERA_FP_MATRIX_MULT Signals
UG-01058
2014.12.19
Altera Corporation
ALTERA_FP_MATRIX_MULT IP Core
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About Floating-Point IP Cores 7
- Design Flow 8
- Using the Parameter Editor 10
- File Name Description 12
- Upgrading IP Cores 15
- Related Information 18
- Floating-Point Formats 19
- Special Case Numbers 20
- Non-IEEE-754 Standard Format 21
- Integer bits 22
- Fraction bits 22
- VHDL Component Declaration 24
- VHDL LIBRARY-USE Declaration 24
- ALTERA_FP_MATRIX_INV IP Core 25
- Triangular Matrix Inversion 29
- Matrix Multiplication 29
- Matrix Inversion Operation 29
- Precision Format Numbers 30
- Sample Matrix Data 32
- Matrix Data 33
- ALTERA_FP_MATRIX_INV Signals 34
- ALTERA_FP_MATRIX_MULT IP Core 36
- . . . N-10 . . 38
- . . . N-10 38
- ALTERA_FP_MATRIX_MULT 39
- Parameter Value Description 40
- ALTERA_FP_ACC_CUSTOM IP Core 42
- ALTERA_FP_ACC_CUSTOM Signals 44
- ALTFP_ADD_SUB IP Core 48
- ALTFP_ADD_SUB Signals 51
- ALTFP_ADD_SUB 52
- ALTFP_ADD_SUB Parameters 53
- ALTFP_DIV IP Core 55
- ALTFP_DIV Truth Table 56
- ALTFP_DIV Signals 60
- ALTFP_DIV Parameters 61
- ALTFP_MULT IP Core 63
- Parameters 66
- ALTFP_MULT Signals 67
- ALTFP_SQRT 69
- ALTFP_SQRT Truth Table 70
- ALTFP_SQRT Signals 72
- ALTFP_SQRT Parameters 74
- ALTFP_EXP IP Core 75
- ALTFP_EXP Signals 78
- ALTFP_EXP 79
- ALTFP_EXP Parameters 80
- ALTFP_INV IP Core 81
- ALTFP_INV_SQRT IP Core 87
- ALTFP_INV_SQRT 90
- ALTFP_LOG 93
- ALTFP_ATAN IP Core 99
- ALTFP_ATAN Parameters 100
- Parameter 101
- Type Required Description 101
- ALTFP_SINCOS IP Core 102
- ALTFP_SINCOS Signals 103
- ALTFP_SINCOS Parameters 104
- ALTFP_ABS IP Core 105
- UG-01058 106
- 2014.12.19 106
- ALTFP_ABS Signals 107
- ALTFP_ABS 108
- ALTFP_ABS Parameters 109
- ALTFP_COMPARE IP Core 111
- Format Numbers 112
- ALTFP_COMPARE Signals 113
- ALTFP_COMPARE Parameters 114
- ALTFP_CONVERT IP Core 116
- ALTFP_CONVERT Output Latency 117
- Point Format Numbers 121
- Time Event 122
- ALTFP_CONVERT Signals 123
- ALTFP_CONVERT Parameters 125
- ALTERA_FP_FUNCTIONS IP Core 128
- Function Description 129
- ALTERA_FP_FUNCTIONS Signals 151
- Altera Corporation 152
- Send Feedback 152
- Document Revision History 156
- Date Document 157
- Changes Made 157
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