Altera DE2-115 Bedienungsanleitung PDF herunterladen (Seite 65)

Figure 4-33 Connections between FPGA and SRAM

 SDRAM

The board features 128MB of SDRAM, implemented using two 64MB SDRAM devices. Each

device consists of separate 16-bit data lines connected to the FPGA, and shared control and address

lines. These chips use the 3.3V LVCMOS signaling standard. Connections between FPGA and

SDRAM are shown in Figure 4-34.

Figure 4-34 Connections between FPGA and SDRAM

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Altera DE2-115 Bedienungsanleitung Seite 65