Altera DE2-115 Bedienungsanleitung PDF herunterladen (Seite 57)

Figure 4-26 Y-Cable use for both Keyboard and Mouse

Table 4-19 PS/2 Pin Assignments

Signal Name FPGA Pin No. Description I/O Standard

PS2_CLK PIN_G6 PS/2 Clock 3.3V

PS2_DAT PIN_H5 PS/2 Data 3.3V

PS2_CLK2 PIN_G5 PS/2 Clock (reserved for second PS/2 device) 3.3V

PS2_DAT2 PIN_F5 PS/2 Data (reserved for second PS/2 device) 3.3V

The DE2-115 board provides Ethernet support via two Marvell 88E1111 Ethernet PHY chips. The

88E1111 chip with integrated 10/100/1000 Mbps Gigabit Ethernet transceiver support

GMII/MII/RGMII/TBI MAC interfaces. Table 4-20 describes the default settings for both chips.

Figure 4-27 shows the connection setup between the Gigabit Ethernet PHY (ENET0) and FPGA.

Table 4-20 Default Configuration for Gigabit Ethernet

Configuration Description Default Value

PHYADDR[4:0] PHY Address in MDIO/MDC Mode

10000 for Enet0;10001 for Enet1

ENA_PAUSE Enable Pause 1-Default Register 4.11:10 to 11

ANEG[3:0]

Auto negotiation configuration

for copper modes

1110-Auto-neg, advertise all capabilities, prefer

master

ENA_XC Enable Crossover 0-Disable

DIS_125 Disable 125MHz clock 1-Disable 125CLK

HWCFG[3:0] Hardware Configuration Mode 1011/1111 RGMII to copper/GMII to copper

DIS_FC Disable fiber/copper interface 1-Disable

DIS_SLEEP Energy detect 1-Disable energy detect

SEL_TWSI Interface select 0-Select MDC/MDIO interface

INT_POL Interrupt polarity 1-INTn signal is active LOW

75/50OHM Termination resistance 0-50 ohm termination for fiber

Here only RGMII and MII modes are supported on the board (The factory default mode is RGMII).

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Altera DE2-115 Bedienungsanleitung Seite 57