Altera DE2-70 Spezifikationen PDF herunterladen (Seite 9)

The CAD ﬂow involves the following steps:

Design Entry – the desired circuit is speciﬁed either by means of a schematic diagram, or by using a

hardware description language, such as Verilog or VHDL.

Synthesis – the entered design is synthesized into a circuit that consists of the logic elements (LEs)

provided in the FPGA chip

Functional Simulation – the synthesized circuit is tested to verify its functional correctness; this

simulation does not take into account any timing issues

Fitting – the CAD Fitter tool determines the placement of the LEs deﬁned in the netlist into the LEs in

an actual FPGA chip; it also chooses routing wires in the chip to make the required connections between

speciﬁc LEs.

Timing Analysis – propagation delays along the various paths in the ﬁtted circuit are analyzed to provide

an indication of the expected performance of the circuit.

Timing Simulation – the ﬁtted circuit is tested to verify both its functional correctness and timing

Programming and Conﬁguration – the designed circuit is implemented in a physical FPGA chip by pro-

gramming the conﬁguration switches that conﬁgure the LEs and establish the required wiring

connections.

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Altera DE2-70 Spezifikationen Seite 9