Altera Video and Image Processing Suite Bedienungsanleitung PDF herunterladen (Seite 90)

Signal Direction Description

vid_hd_sdn Input Clocked video color plane format selection signal . This

signal distinguishes between sequential (when low) and

parallel (when high) color plane formats.

Note: For run-time switching of color plane

transmission formats mode only.

vid_std Input Video standard bus. Can be connected to the rx_std

signal of the SDI IP core (or any other interface) to read

from the Standard register.

sof Output Start of frame signal. A change of 0 to 1 indicates the start

of the video frame as configured by the SOF registers.

Connecting this signal to a CVO IP core allows the

function to synchronize its output video to this signal.

sof_locked Output Start of frame locked signal. When asserted, the sof signal

is valid and can be used.

refclk_div Output A single cycle pulse in-line with the rising edge of the h

sync.

overflow Output Clocked video overflow signal. A signal corresponding to

the overflow sticky bit of the Status register synchronized

to vid_clk. This signal is for information only and no

action is required if it is asserted.

Note: Present only if you turn on Use control port.

vid_hdmi_duplication[3:0] Input If you select Remove duplicate pixels in the parameter,

this 4-bit bus is added to the CVI II interface. You can

drive this bus based on the number of times each pixel is

duplicated in the stream (HDMI-standard compliant).

Table 4-18: Clocked Video Output Signals

Signal Direction Description

rst Input The IP core asynchronously resets when you assert this

signal. You must deassert this signal synchronously to the

rising edge of the clock signal.

Note: When the video in and video out do not use the

same clock, this signal is resynchronized to the

output clock to be used in the output clock

domain.

is_clk Input Clock signal for Avalon-ST ports dout and control. The

IP core operates on the rising edge of the is_clk signal.

is_data Input dout port Avalon-ST data bus. This bus enables the

transfer of pixel data into the IP core.

UG-VIPSUITE

2015.05.04

Clocked Video Interface Signals

4-31

Clocked Video Interface IP Cores

Altera Corporation

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