Altera Video and Image Processing Suite Bedienungsanleitung Seite 51
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Figure 2-17: Timing Diagram Showing R’G’B’ Transferred in Sequence
The figure shows how a number of pixels from the middle of a frame are processed.
clock
din_ready
din_valid
din_data 7:0
R
m,n
R
G
0,0
G
m,n
B
m,n
B
m+1,n
1.
2.
3.
4.
5. 6.
7.
dout_ready
dout_valid
dout_data 7:0
R
8.
9.
G
1,0
G
m+1,n
G
0,0
G
m,n
B
m,n
m+1,n
m,n
This example is similar to example one except that it is configured to accept data in sequence rather than
parallel. The signals shown in the timing diagram are therefore the same but with the exception that the
two data ports are only 8 bits wide.
The sequence of events for this example:
1. Initially, din_ready is logic '1'. The source driving the input port sets din_valid to logic '1' and puts
the blue color value B
m,n
on the din_data port.
2. The source holds din_valid at logic '1' and the green color value G
m,n
is input.
3. The corresponding red color value R
m,n
is input.
4. The IP core sets dout_valid to logic '1' and outputs the blue color value of the first processed color
sample on the dout_data port. Simultaneously the sink connected to the output port sets dout_ready
to logic '0'. The Avalon Interface Specifications state that sinks may set ready to logic '0' at any time, for
example because the sink is a FIFO and it has become full.
5. The IP core sets dout_valid to logic '0' and stops putting data on the dout_data port because the sink
is not ready for data. The IP core also sets din_ready to logic '0' because there is no way to output data
and the IP core must stop the source from sending more data before it uses all internal buffer space.
The sink holds din_valid at logic '1' and transmits one more color sample G
m+1,n
, which is legal
because the ready latency of the interface means that the change in the IP core's readiness does not take
effect for one clock cycle.
6. Both the input and output interfaces do not transfer any data: the IP core stalls to wait for the sink.
7. The sink sets dout_ready to logic '1'. This could be because space has been cleared in a FIFO.
8. The IP core sets dout_valid to logic '1' and resumes transmitting data. Now that the flow of data is
unimpeded again, it sets din_ready to logic '1'.
9. The source responds to din_ready by setting din_valid to logic '1' and resuming data transfer.
2-24
Packet Transfer Examples
UG-VIPSUITE
2015.05.04
Altera Corporation
Interfaces
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Feature Support 7
- Release Information 9
- Device Family Support 10
- IP Core Mode Latency 11
- Interfaces 28
- Video Formats 29
- D0 D1vid_data 32
- Signal Name Description 33
- Avalon-ST Video Protocol 34
- Video Data Packets 38
- Symbol transmitted first 39
- Symbol transmitted last 39
- Plane for even rows 40
- Plane for odd rows 40
- Control Data Packets 42
- Parameters 43
- Description 43
- Type Width Height Interlacin 43
- Order Symbol Order Symbol 45
- Ancillary Data Packets 46
- Packet Propagation 46
- Parameter Name Value 47
- Signal Width Direction 47
- Packet Transfer Examples 48
- Parameter Value 50
- Avalon-MM Slave Interfaces 52
- Avalon-MM Master Interfaces 55
- Related Information 56
- Getting Started 57
- OpenCore Plus IP Evaluation 59
- Control Port 60
- Format Description 61
- Interrupts 64
- Generator Lock 68
- Underflow and Overflow 70
- Timing Constraints 71
- Handling Ancillary Packets 71
- Modules Description 75
- Address Register Description 100
- UG-VIPSUITE 105
- 2015.05.04 105
- 2D FIR Filter IP Core 106
- Coefficient Precision 107
- Parameter Value Description 108
- 2D FIR Filter Signals 109
- Signal Direction Description 110
- Video Mixing IP Cores 112
- Alpha Blending 113
- Video Mixing Signals 116
- 20 Input 3 enable 121
- Chroma Resampler IP Core 122
- 4:4:4 to 4:2:2 123
- 4:2:2 to 4:4:4 123
- Vertical Resampling (4:2:0) 124
- Chroma Resampler Signals 126
- Video Clipping IP Cores 127
- Video Clipping Signals 130
- Color Plane Sequencer IP Core 135
- Rearranging Color Patterns 136
- Splitting and Duplicating 137
- Subsampled Data 138
- Color Plane Sequencer Signals 139
- IP Cores Feature 141
- Input and Output Data Types 142
- Color Space Conversion 142
- Operands 145
- Control Synchronizer IP Core 153
- Control Synchronizer Signals 157
- Deinterlacing IP Cores 160
- Deinterlacing Methods 161
- Bob with Scanline Duplication 162
- Motion-Adaptive 162
- Sobel-Based HQ Mode 164
- Frame Buffering 165
- Types Description 166
- Frame Rate Conversion 167
- Altera Corporation 168
- Send Feedback 168
- Deinterlacing Signals 176
- Register Address 190
- (Decimal) 190
- Register Suggested 190
- Settings 190
- Comments 190
- Tuning Motion Shift 191
- Frame Reader IP Core 192
- Frame Reader Signals 194
- Frame Buffer IP Cores 198
- Double Buffering 199
- Triple Buffering 199
- Locked Frame Rate Conversion 200
- Color Format 201
- Frame Buffer Signals 206
- Gamma Corrector IP Core 214
- Gamma Corrector Signals 215
- Interlacer IP Core 218
- Interlacer Parameter Settings 219
- Interlacer Signals 219
- Interlacer Control Registers 221
- Scaler II IP Core 222
- Bilinear Algorithm 223
- Double-Buffering 226
- Scaler II Parameter Settings 230
- Scaler II Signals 233
- Scaler II Control Registers 235
- Video Switching IP Cores 237
- Mixer Layer Switching 238
- Video Switching Signals 239
- Test Pattern 243
- Trace System IP Core 253
- Trace System Signals 255
- Trace Within System Console 258
- TCL Shell Commands 259
- Command Arguments Function 260
- Packet Visualization 263
- Monitor Settings 264
- Subscribe 269
- Avalon-ST Video Class Library 270
- Class Description 272
- Running the Tests 275
- Video File Reader Test 278
- Example Test Environment 281
- Video Field Life Cycle 282
- Constrained Random Test 283
- Code for Scoreboards 285
- Code for to_grey Function 286
- Complete Class Reference 287
- Method Call Description 288
- Member Description 288
- Raw Video Data Format 299
- Y 410 / A 2R 10 G 10 B 10 301
- Additional Information 306
- Date Version Changes 307
- How to Contact Altera 310
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