Altera V-Series Avalon-MM DMA Bedienungsanleitung Seite 22
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Parameter Settings
3
2014.12.18
UG-01154
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System Settings
Table 3-1: System Settings for PCI Express
Parameter Value Description
Number of Lanes x1, x2, ×4, ×8 Specifies the maximum number of lanes supported. Avalon-
MM Interface with DMA does not support x1 configurations.
Lane Rate Gen1 (2.5 Gbps)
Gen2 (2.5/5.0 Gbps)
Gen3 (2.5/5.0/8.0
Gbps)
Specifies the maximum data rate at which the link can operate.
Application
interface width
128-bit
256-bit
Specifies the width of the interface to the Application Layer.
The following table indicates the possible combinations.
Application
Interface Width
Configuration Application Layer
Clock Frequency
128 bits Gen1 x8 125 MHz
128 bits Gen2 x4 125 MHz
128 bits Gen2 x8 250 MHz
256 bits Gen2 x8 125 MHz
128 bits Gen3 x4 250 MHz
256 bits Gen3 x4 125 MHz
256 bits Gen3 x8 250 MHz
RX Buffer credit
allocation -
Minimum
Low
Determines the allocation of posted header credits, posted
data credits, non-posted header credits, completion header
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- User Guide 1
- Features 3
- Interface 5
- Release Information 8
- Example Designs 9
- Debug Features 9
- IP Core Verification 9
- Related Information 10
- Altera Corporation 11
- Datasheet 11
- Send Feedback 11
- Parameter Value 17
- Directory Description 18
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 20
- Parameter Settings 22
- Parameter Value Description 23
- Device Capabilities 28
- Error Reporting 28
- Link Capabilities 29
- MSI and MSI-X Capabilities 29
- Power Management 30
- PCIe Address Space Settings 31
- RX Master Module 36
- TX Slave Module 38
- Signal Name Directio 39
- Description 39
- Bits Name Description 41
- Clock Signals 45
- Signal Direction Description 46
- MSI Interrupts for Endpoints 51
- Serial Data Signals 53
- 9 Ch 18 Ch 54
- PIPE Interface Signals 64
- Test Signals 68
- Registers 70
- Altera-Defined VSEC Registers 77
- CvP Registers 78
- Bits Register Description 82
- Register Access Description 86
- Read DMA Example 91
- Byte Offset 95
- Register Dir Description 95
- Reset and Clocks 100
- Example Design 101
- Hard IP for PCI Express 101
- UG-01154 102
- 2014.12.18 102
- Clock Domains 104
- Data Rate Frequency 105
- Clock Summary 106
- Error Handling 107
- Physical Layer Errors 108
- Data Link Layer Errors 108
- Transaction Layer Errors 109
- Error Type Description 110
- Status Bit Conditions 112
- IP Core Architecture 114
- Hard IP for PCI Express 115
- Top-Level Interfaces 116
- Avalon-MM DMA Interface 116
- Clocks and Reset 116
- Transceiver Reconfiguration 116
- Interrupts 116
- Data Link Layer 117
- Physical Layer 119
- TX Packets 120
- Altera FPGA 122
- Qsys System 123
- Subscribe 125
- Address[31:2] 130
- Figure A-6: I/O Read Request 132
- Additional Information 136
- Date Version Changes Made 137
- How to Contact Altera 139
- Typographic Conventions 140
- Visual Cue Meaning 141
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