Altera V-Series Avalon-MM DMA Bedienungsanleitung Seite 105

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The PCI Express Base Specification requires that the refclk signal frequency be 100 MHz ±300 PPM.
The transitions between Gen1, Gen2, and Gen3 should be glitchless. pclk can be turned off for most of
the 1 ms timeout assigned for the PHY to change the clock rate; however, pclk should be stable before the
1 ms timeout expires.
The transitions between Gen1 and Gen2 should be glitchless. pclk can be turned off for most of the 1 ms
timeout assigned for the PHY to change the clock rate; however, pclk should be stable before the 1 ms
timeout expires.
Table 6-2: pclk Clock Frequency
Data Rate Frequency
Gen1 250 MHz
Gen2 500 MHz
The CDC module implements the asynchronous clock domain crossing between the PHY/MAC pclk
domain and the Data Link Layer coreclk domain. The transceiver pclk clock is connected directly to the
Hard IP for PCI Express and does not connect to the FPGA fabric.
Related Information
PCI Express Base Specification 2.1 or 3.0
coreclkout_hip
coreclkout_hip
Table 6-3: Application Layer Clock Frequency for All Combinations of Link Width, Data Rate and
Application Layer Interface Widths
The coreclkout_hip signal is derived from pclk. The following table lists frequencies for coreclkout_hip,
which are a function of the link width, data rate, and the width of the Application Layer to Transaction Layer
interface. The frequencies and widths specified in this table are maintained throughout operation. If the link
downtrains to a lesser link width or changes to a different maximum link rate, it maintains the frequencies it was
originally configured for as specified in this table. (The Hard IP throttles the interface to achieve a lower
throughput.)
Link Width Max Link Rate Avalon Interface Width coreclkout_hip
×8 Gen1 128 125 MHz
×4 Gen2 128 125 MHz
×8 Gen2 128 250 MHz
×8 Gen2 256 125 MHz
×4 Gen3 128 250 MHz
6-6
coreclkout_hip
UG-01154
2014.12.18
Altera Corporation
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