Altera Stratix V GX FPGA Development Board Bedienungsanleitung Seite 31
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Chapter 2: Board Components 2–23
Clock Circuitry
October 2014 Altera Corporation Stratix V GX FPGA Development Board
Reference Manual
Clock Circuitry
This section describes the board's clock inputs and outputs.
On-Board Oscillators
The development board includes a 50-MHz, 100-MHz, 125-MHz, and 156.25-MHz
programmable oscillators. Figure 2–5 shows the default frequencies of all external
clocks going to the Stratix V GX FPGA development board.
Figure 2–5. Stratix V GX FPGA Development Board External Clock Inputs and Default Frequencies
SMA
REFCLK INPUT
SMA
Buffer
(100 MHz
Default)
Si570
(100 MHz
Default)
Si5388
156.25 MHz
625 MHz
270 MHz
100 MHz
REFCLK4_QR2_P/N
REFCLK5_QR2_P/N (HSMB)
REFCLK2_QR1_P/N (HSMB)
REFCLK1_QR0_P/N (HSMA)
REFCLK0_QR0_P/N (HSMA)
644.53125 MHz
282.5 MHz
125 MHz
125 MHz
125 MHz
100 MHz
100 MHz
100 MHz
100 MHz
CLK4
CLK0
CLK6
CLK22
CLK16
CLK9
REFCLK5_QL2_P/N (148.5 MHz)
SDI (148.5 M / 148.35 M)
REFCLK4_QL2_P/N (QSFP)
REFCLK2_QL1_P (QSFP)
REFCLK1_QL0_P/N
PCIE_REF_CLK_P/N
CLKINTOP_P/N[1]
CLKINTOP_P/N[0]
CLKIN_50
CLKINBOT_P/N[0]
CLK_125_P/N
CLKINBOT_P/N[1]
Si5388
CLK3
CLK2
CLK1
CLK0
Si571
148.5 MHz
Default
B8
QL2
QL1
QL0
B3
B4
B7
QR2
QR1
QR0
CLK3
CLK2
CLK1
CLK0
50 M
125 M
- Reference Manual 1
- Contents 3
- Additional Information 4
- 1. Overview 5
- Board Component Blocks 6
- Chapter 1: Overview 1–3 7
- Handling the Board 8
- 2. Board Components 9
- Board Overview 10
- I/O Resources 13
- MAX V CPLD System Controller 14
- Configuration 20
- Figure 2–3. JTAG Chain 22
- Note to Table 2–9: 24
- Figure 2–4. PFL Configuration 25
- Status LEDs 26
- Board Settings DIP Switch 27
- JTAG Control DIP Switch 28
- MAX V Reset Push Button 29
- Program Load Push Button 29
- Program Select Push Button 30
- CPU Reset Push Button 30
- Clock Circuitry 31
- Off-Board Clock Input/Output 33
- General User Input/Output 34
- User-Defined DIP Switches 35
- General User-Defined LEDs 36
- HSMC User-Defined LEDs 37
- Components and Interfaces 39
- CROSS MAX 40
- CROSS MIN 40
- 10/100/1000 Ethernet 42
- SDI Video Output/Input 51
- 40G QSFP Connector 53
- RLDRAM II 61
- Power Supply 65
- Power Measurement 67
- Temperature Sense 68
- Notes to Table 2–63: 69
- A. Board Revision History 71
- Document Revision History 74
- Note to Table: 75
- Typographic Conventions 76
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