Altera Stratix V Avalon-MM Interface for PCIe Solutions Bedienungsanleitung Seite 181
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Date Version Changes Made
2013.05.06 13.0 • Added support for Configuration Space Bypass Mode, allowing
you to design a custom Configuration Space and support multiple
functions
• Added preliminary support for a Avalon-MM 256-Bit Hard IP for
PCI Express that is capable of running at the Gen3 ×8 data rate.
This new IP Core. Refer to the Avalon-MM 256-Bit Hard IP for
PCI Express User Guide for more information.
• Added Gen3 PIPE simulation support.
• Added support for 64-bit address in the Avalon-MM Hard IP for
PCI Express IP Core, making address translation unnecessary
• Added instructions for running the Single Dword variant.
• Timing models are now final.
• Updated the definition of refclk to include constraints when CvP
is enabled.
• Added section covering clock connectivity for reconfiguration
when CvP is enabled.
• Corrected access field in Root Port TLP Data registers.
• Added Getting Started chapter for Configuration Space Bypass
mode.
• Added signal and register descriptions for the Gen3 PIPE
simulation.
• Added 64-bit addressing for the Avalon-MM IP Cores for PCI
Express.
• Changed descriptions of rx_st_err[1:0], tx_st_err[1:0], rx_
st_valid[1:0], and tx_st_valid[1:0] buses. Bit 1 is not used.
• Corrected definitions of RP_RXCPL_STATUS.SOP and RP_RXCPL_
STATUS.EOP bits. SOP is 0x2010, bit[0] and EOP is 0x2010, bit[1].
• Improved explanation of relaxed ordering of transactions and
provided examples.
• Revised discussion of Transceiver Reconfiguration Controller IP
Core. Offset cancellation is not required for Gen1 or Gen2
operation.
• Removed reconfig_busy port from connect between PHY IP
Core for PCI Express and the Transceiver Reconfiguration
Controller in the Altera Transceiver Reconfiguration Controller
Connectivity figure. The Transceiver Reconfiguration Controller
drives reconfig_busy port to the Altera PCIe Reconfig Driver.
2011.07.30
11.01 Corrected typographical errors.
2011.05.06 11.0 First release.
UG-01097_avmm
2014.12.15
Revision History for the Avalon-MM Interface
C-5
Additional Information
Altera Corporation
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- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Altera FPGA 8
- Debug Features 10
- IP Core Verification 10
- Recommended Speed Grades 11
- Running Qsys 14
- Generating the Example Design 15
- Simulating Altera Designs 17
- Time TLP Type Payload 18
- TLP Header 18
- Creating a Quartus II Project 19
- Compiling the Design 19
- Programming a Device 20
- Parameter Settings 21
- Parameter Value Description 22
- Device Capabilities 25
- Error Reporting 26
- Link Capabilities 27
- MSI and MSI-X Capabilities 28
- Power Management 29
- Clock Domains on page 6-5 33
- Application Layer 34
- RX Avalon-MM Master Signals 36
- Clock Signals 41
- Signal Direction Description 42
- Variant Logical Interfaces 49
- Hard IP Status Extension 50
- Field and Bit Map 58
- 0134678951 58
- Bit(s) Field Description 59
- Serial Data Signals 60
- PIPE Interface Signals 64
- Test Signals 69
- Registers 70
- Altera-Defined VSEC Registers 78
- CvP Registers 79
- Address Range Register 83
- Bit Name Access Description 84
- Bits Name Access Description 85
- PCI Express Mailbox Registers 86
- Avalon-MM Mailbox Registers 90
- Address Name Access 91
- Description 91
- Byte Offset 91
- Register Dir Description 91
- Sending a Write TLP 97
- Root Port TLP Data Registers 99
- UG-01097_avmm 100
- 2014.12.15 100
- Related Information 101
- Bits Register Description 102
- Reset and Clocks 105
- Hard IP for PCI Express 106
- Example Design 106
- Clock Domains 109
- Data Rate Frequency 110
- Clock Summary 112
- Interrupts for Endpoints 113
- MSI/MSI‑X Support 115
- MsiIntfc_o[81:0] 116
- MsiControl_o[15:0] 116
- MsixIntfc_o[15:0] 116
- IntxReq_i 116
- IntxAck_o 116
- Error Handling 117
- Physical Layer Errors 118
- Data Link Layer Errors 118
- Transaction Layer Errors 119
- Error Type Description 120
- Status Bit Conditions 123
- IP Core Architecture 125
- Hard IP for PCI Express 126
- Top-Level Interfaces 127
- Avalon-MM Interface 127
- Clocks and Reset 127
- Transceiver Reconfiguration 127
- Interrupts 127
- Data Link Layer 128
- Altera Corporation 129
- Send Feedback 129
- Physical Layer 130
- TX Packets 131
- Avalon‑MM Bridge TLPs 135
- Byte Enable Value Description 136
- PCI Express Avalon-MM Bridge 138
- RX Block 144
- Avalon-MM RX Master Block 144
- TX Block 145
- Interrupt Handler Block 145
- Enable PLL calibration 147
- Throughput Optimization 151
- Throughput of Posted Writes 153
- Design Implementation 155
- CONF_DONE 156
- Endpoint Reset 156
- Root Port Reset 156
- SDC Timing Constraints 157
- Optional Features 159
- ECRC on the RX Path 160
- ECRC on the TX Path 161
- Debugging 163
- Setting Up Simulation 166
- Use Third-Party PCIe Analyzer 168
- BIOS Enumeration Issues 168
- Address[31:2] 169
- Figure A-6: I/O Read Request 171
- 7 6 5 4 3 2 1 0 175
- Core Config 8 4 1 175
- Additional Information 177
- Date Version Changes Made 178
- How to Contact Altera 182
- Typographic Conventions 182
- Visual Cue Meaning 183
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