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7–60 User Guide Version 11.1 Altera Corporation

PCI Compiler October 2011

Control & Status Registers

Avalon-MM Interrupt Enable Register

An Avalon-MM interrupt can be signaled for any of the conditions noted

in the Avalon Interrupt Status Register by setting the corresponding bits

in the Avalon Interrupt Enable Register (Table 7–28).

PCI interrupts can also be enabled for all of the error conditions in bits

13:8 and 2:0. However, only one of the Avalon-MM or PCI interrupts (not

both) should be enabled for any given bit. There is typically a single

process in either the PCI or Avalon-MM domain that is responsible for

handling the condition reported by the interrupt.

Avalon Mailbox Register Access

A processor local to the interconnect (or any processor not on the PCI bus

attached to the bridge) typically needs write access to a set of

Avalon-to-PCI mailbox registers and read-only access to a set of

PCI-to-Avalon mailbox registers. The specific number (1 or 8) of each of

these types of mailbox registers available is shown in Table 7–1 on

page 7–5.

Table 7–28. Avalon Interrupt Enable Register

Avalon Interrupt Enable Register Address 0x3070

Bit Name

Access

Mode

Description

31:0 One-to-one enable mapping for the

bits in the Avalon-MM interrupt status

RW When set to 1 indicates the setting of the

associated bit in the Avalon-MM interrupt status

(

CraIrq_o) to be asserted.

Only bits implemented in the Avalon-MM

interrupt status register are implemented in the

enable register. Unimplemented bits cannot be

set to 1.

1 2 ... 323 324 325 326 327 328 329 330 331 332 333 ... 359 360

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Altera PCI Compiler Bedienungsanleitung Seite 328