Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core Bedienungsanleitung PDF herunterladen (Seite 10)

Parameter Type Condition Description

fbclk Input Optional

The external feedback input port for the I/O

PLL.

The Altera IOPLL IP core creates this port when

the I/O PLL is operating in external feedback

mode or zero-delay buffer mode. To complete

the feedback loop, a board-level connection must

connect the fbclk port and the external clock

output port of the I/O PLL.

fboutclk Output Optional

The port that feeds the fbclk port through the

mimic circuitry.

The fboutclk port is available only if the I/O

PLL is in external feedback mode.

zdbfbclk Bidirectional Optional

The bidirectional port that connects to the

mimic circuitry. This port must connect to a

bidirectional pin that is placed on the positive

feedback dedicated output pin of the I/O PLL.

The zdbfbclk port is available only if the I/O

PLL is in zero-delay buffer mode.

locked Output Optional The Altera IOPLL IP core drives this port high

when the PLL acquires lock. The port remains

high as long as the IOPLL is locked. The I/O PLL

asserts the locked port when the phases and

frequencies of the reference clock and feedback

clock are the same or within the lock circuit

tolerance. When the difference between the two

clock signals exceeds the lock circuit tolerance,

the I/O PLL loses lock.

refclk1 Input Optional Second reference clock source that drives the I/O

PLL for clock switchover feature.

extswitch Input Optional Assert the extswitch signal high (1’b1) for at

least 3 clock cycles to manually switch the clock.

activeclk Output Optional Output signal to indicate which reference clock

source is in used by I/O PLL.

clkbad Output Optional Output signal that indicates the status of

reference clock source is good or bad.

cascade_out Output Optional Output signal that feeds into downstream I/O

PLL.

adjpllin Input Optional Input signal that feeds from upstream I/O PLL.

outclk_[] Output Optional Output clock from I/O PLL.

Ports

UG-01155

2015.05.04

Altera Corporation

Altera I/O Phase-Locked Loop (Altera IOPLL) IP Core User Guide

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