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Note: The CLK_HR frequency must be half the frequency of CLK_FR. If the clocks are driven by IOPLL,

you may consider using the derive_pll_clocks SDC command.

Single Data Rate Output Register

Figure 13: Single Data Rate Output Register

These SDC commands generate the source clock and the output clock to be transmitted:

create_clock -name sdr_out_clk -period "100 MHz" sdr_out_clk

create_generated_clock -source sdr_out_clk -name sdr_out_outclk sdr_out_outclk

This SDC command instructs the TimeQuest timing analyzer to analyze the output data to be transmitted

against the output clock to be transmitted.

set_output_delay -clock sdr_out_clk 0.45 sdr_out_data

DDIO Output Register

The output side of the full-rate and half-rate DDIO output register is the same.

create_clock and create_generated_clock

These SDC commands generate the clocks to the DDIO and the clock to be transmitted:

create_clock -name ddio_out_fr_clk -period "200 MHz" ddio_out_fr_clk

create_generated_clock -source ddio_out_fr_clk -name ddio_out_fr_outclk

ddio_out_fr_outclk

ug-altera_gpio

2014.08.18

Single Data Rate Output Register

Altera GPIO IP Core User Guide

Altera Corporation

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Altera GPIO Bedienungsanleitung Seite 19