Altera Designing With Low-Level Primitives Bedienungsanleitung PDF herunterladen (Seite 49)

Altera Corporation 2–27

April 2007 Designing with Low-Level Primitives User Guide

Primitive Reference

Example 2–17. ALT_BIDIR_BUF Primitive, VHDL Component Declaration

component ALT_BIDIR_BUF

generic (

IO_STANDARD : STRING := "none";

LOCATION : STRING := "none";

ENABLE_BUS_HOLD : STRING := "none";

WEAK_PULL_UP_RESISTOR : STRING := "none";

SLEW_RATE : STRING := "none";

CURRENT_STRENGTH : STRING := "none";

INPUT_TERMINATION : STRING := "none";

OUTPUT_TERMINATION : STRING := "none";

TERMINATION : STRING := "none"

);

port (

bidirin : inout std_logic;

oe: in std_logic;

io : inout std_logic;

);

end component;

LCELL

The instantiation of an LCELL primitive buffer allocates one logic cell for

your design. When you instantiate an LCELL buffer in your design, the

Quartus II software preserves the assignment and does not remove it

during the synthesis process. The name that you assign the LCELL is also

preserved.

You should not use

LCELL primitives to create an intentional delay or

asynchronous pulse in your design. The delay of these elements varies

with temperature, power supply voltage, and device fabrication process.

Race conditions may occur that result in an unreliable circuit.

When you turn on the Implement as Output of Logic Cell option, or use

the synthesis attribute KEEP, an LCELL buffer is automatically inserted

by the Quartus II synthesis engine into your design.

Example 2–18 shows a Verilog HDL example of an LCELL primitive

instantiation.

Example 2–18. LCELL Primitive Instantiation, Verilog HDL

lcell <instance_name> (.in(<input_wire>), .out(<output_wire>);

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Altera Designing With Low-Level Primitives Bedienungsanleitung Seite 49