Altera DDR Timing Wizard Bedienungsanleitung Seite 91
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Altera Corporation 3–31
November 2007 DDR Timing Wizard User Guide
Using the dtw_timing_analysis.tcl Script
To avoid assigning these resynchronization registers’ locations manually,
you can use a tcl script called relative_constraint.tcl. This script is
available with the Legacy_PHY.qpf example design that is downloadable
with AN328: Interfacing DDR2 SDRAM in Stratix II, Stratix II GX, and Arria
GX Devices, and is also included in Quartus II 7.2 SP1 and later releases in
the Quartus II installation direcory (common/tcl/apps/relcon).
f For more information on the script, please refer to Appendix E of AN328:
Interfacing DDR2 SDRAM in Stratix II, Stratix II GX, and Arria GX Devices.
The example design in AN328: Interfacing DDR2 SDRAM in Stratix II,
Stratix II GX, and Arria GX Devices uses two batch files, called resynch.bat
and core_registers.bat. The resynch.bat file aligns the resynchronization
registers to the same column as the pin feeding them, as the DQ pin
locations were changed from the default assignments due to the board
pin-outs. The core_registers.bat places the second resynchronization
registers and the intermediate resynchronization registers closer to the
pins to meet core timing.
Both batch files use –pin_range and –reg_range argument since one
pin is actually related to two registers (due to the double-data rate
transfer). An example of the code in the resynch.bat file is shown below
where each DQ group (in this care ddr2_dq[7:0]) is called twice to be
associated with the resynchronization registers with index [7:0] and
with index [15:8]:
quartus_sh -t relative_constraint.tcl -project
Legacy_PHY -pin_name *ddr2_dq[* -reg_name
"*0:*|resynched_data[*]" -show_regs -reg_range 7:0
-pin_range 7:0 -row_offset 1 -apply
quartus_sh -t relative_constraint.tcl -project
Legacy_PHY -pin_name *ddr2_dq[* -reg_name
"*0:*|resynched_data[*]" -show_regs -reg_range 15:8
-pin_range 7:0 -row_offset 1 -apply
Note that you need to distinguish the resynchronization registers by
group, hence the use of "0" in the wildcard, or else the
relative_constraint.tcl script grabs all the registers with
"resynched_data" as part of the name (which equals to 144 registers in
this example).
If you have multiple memory controllers in the design, you also need to
distinguish the name of each controller so that the registers get the correct
placement by the script.
- DDR Timing Wizard 1
- Table of Contents 3
- November 2007 4
- About this User Guide 5
- Typographic 6
- Conventions 6
- 1. About the DDR Timing 7
- Device Family 8
- 1–4 Altera Corporation 10
- Introduction 10
- Altera Corporation 1–5 11
- About the DDR Timing Wizard 11
- Note to Figure 1–1: 11
- Features 12
- 2. Getting Started 13
- Design Flow 14
- 2–2 Altera Corporation 14
- Altera Corporation 2–3 15
- Getting Started 15
- 2–4 Altera Corporation 16
- Launching the 17
- DDR Timing 17
- Entering and 18
- Editing Inputs to 18
- Recommended Data Path 19
- 2–8 Altera Corporation 20
- Altera Corporation 2–9 21
- 2–10 Altera Corporation 22
- Altera Corporation 2–11 23
- 2–12 Altera Corporation 24
- Altera Corporation 2–13 25
- Synchronous Systems 26
- Altera Corporation 2–15 27
- (Figure 2–10) 28
- Altera Corporation 2–17 29
- 2–18 Altera Corporation 30
- Analysis & Synthesis 31
- 2–20 Altera Corporation 32
- Altera Corporation 2–21 33
- 2–22 Altera Corporation 34
- Click Next 35
- 2–24 Altera Corporation 36
- Altera Corporation 2–25 37
- 2–26 Altera Corporation 38
- Altera Corporation 2–27 39
- 2–28 Altera Corporation 40
- Altera Corporation 2–29 41
- Altera Corporation 2–31 43
- 200 MHz) 44
- Altera Corporation 2–33 45
- 2–34 Altera Corporation 46
- Altera Corporation 2–35 47
- 2–36 Altera Corporation 48
- Altera Corporation 2–37 49
- 2–38 Altera Corporation 50
- Altera Corporation 2–39 51
- 2–40 Altera Corporation 52
- Altera Corporation 2–41 53
- 2–42 Altera Corporation 54
- Altera Corporation 2–43 55
- Click Finish 56
- Altera Corporation 2–45 57
- DTW Limitations 58
- 2–48 Altera Corporation 60
- 3. Using the 61
- 3–2 Altera Corporation 62
- -dwz_file <value> 63
- -? or -help 63
- -after_iptb <value> 64
- -auto_adjust_cycles 64
- -extract_tcos <value> 64
- *auk_ddr_datapath 65
- *auk_qdrii_sram_datapath 65
- *auk_rldramii_datapath 65
- -stop_after <value> 66
- -vwf_file_name <value> 66
- -write_side 66
- Altera Corporation 3–7 67
- ■ Timing Summary 67
- Altera Corporation 3–9 69
- ■ Recommended Settings 69
- Timing Closure 72
- Altera Corporation 3–13 73
- Note to Figure 3–6: 73
- DDR2/DDR SDRAM Interfaces 74
- QDRII+/QDRII SRAM Interfaces 74
- RLDRAM II Interfaces 75
- 3–16 Altera Corporation 76
- Timing Closure Process 76
- Altera Corporation 3–17 77
- Analyzer 78
- Altera Corporation 3–19 79
- 3–20 Altera Corporation 80
- Altera Corporation 3–21 81
- 3–22 Altera Corporation 82
- Changing Clock Phase Shift 83
- 3–24 Altera Corporation 84
- Altera Corporation 3–25 85
- Changing Clock Cycles 87
- 3–28 Altera Corporation 88
- Altera Corporation 3–29 89
- 3–30 Altera Corporation 90
- ° phase shift in 90
- Altera Corporation 3–31 91
- Conclusion 92
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