Altera Data Conversion HSMC Bedienungsanleitung PDF herunterladen (Seite 34)

B–2 Appendix B: Pin-Out Information for the Stratix III (3SL150)

Development Board

Data Conversion HSMC Reference Manual © November 2008 Altera Corporation

83 LVDS TX or CMOS I/O bit 6 ADA_OR HSMA_TX_P6 LVDS or 2.5 V AE6

84 LVDS RX or CMOS I/O bit 6 ADB_OR HSMA_RX_P6 LVDS or 2.5 V AF4

85 LVDS TX or CMOS I/O bit 6 ADA_OE HSMA_TX_N6 LVDS or 2.5 V AE5

86 LVDS RX or CMOS I/O bit 6 ADB_OE HSMA_RX_N6 LVDS or 2.5 V AF3

89 LVDS TX or CMOS I/O bit 7 ADA_SPI_CS HSMA_TX_P7 LVDS or 2.5 V AD4

90 LVDS RX or CMOS I/O bit 7 ADB_SPI_CS HSMA_RX_P7 LVDS or 2.5 V AG1

91 LVDS TX or CMOS I/O bit 7 AD_SDIO HSMA_TX_N7 LVDS or 2.5 V AD3

92 LVDS RX or CMOS I/O bit 7 AD_SCLK HSMA_RX_N7 LVDS or 2.5 V AH1

95 LVDS or CMOS clock out FPGA_CLK_A_P HSMA_CLK_OUT_P1 LVDS or 2.5 V V10

96 LVDS or CMOS clock in XT_IN_P HSMA_CLK_IN_P1 LVDS or 2.5 V Y4

97 LVDS or CMOS clock out FPGA_CLK_A_N HSMA_CLK_OUT_N1 LVDS or 2.5 V W9

98 LVDS or CMOS clock in XT_IN_N HSMA_CLK_IN_N1 LVDS or 2.5 V W3

101 LVDS TX or CMOS I/O bit 8 DA13 HSMA_TX_P8 LVDS or 2.5 V AC6

102 LVDS RX or CMOS I/O bit 8 DB13 HSMA_RX_P8 LVDS or 2.5 V AF2

103 LVDS TX or CMOS I/O bit 8 DA12 HSMA_TX_N8 LVDS or 2.5 V AC5

104 LVDS RX or CMOS I/O bit 8 DB12 HSMA_RX_N8 LVDS or 2.5 V AF1

107 LVDS TX or CMOS I/O bit 9 DA11 HSMA_TX_P9 LVDS or 2.5 V AB6

108 LVDS RX or CMOS I/O bit 9 DB11 HSMA_RX_P9 LVDS or 2.5 V AE2

109 LVDS TX or CMOS I/O bit 9 DA10 HSMA_TX_N9 LVDS or 2.5 V AB5

110 LVDS RX or CMOS I/O bit 9 DB10 HSMA_RX_N9 LVDS or 2.5 V AE1

113 LVDS TX or CMOS I/O bit 10 DA9 HSMA_TX_P10 LVDS or 2.5 V AB8

114 LVDS RX or CMOS I/O bit 10 DB9 HSMA_RX_P10 LVDS or 2.5 V AE4

115 LVDS TX or CMOS I/O bit 10 DA8 HSMA_TX_N10 LVDS or 2.5 V AC7

116 LVDS RX or CMOS I/O bit 10 DB8 HSMA_RX_N10 LVDS or 2.5 V AE3

119 LVDS TX or CMOS I/O bit 11 DA7 HSMA_TX_P11 LVDS or 2.5 V Y6

120 LVDS RX or CMOS I/O bit 11 DB7 HSMA_RX_P11 LVDS or 2.5 V AC2

121 LVDS TX or CMOS I/O bit 11 DA6 HSMA_TX_N11 LVDS or 2.5 V Y5

122 LVDS RX or CMOS I/O bit 11 DB6 HSMA_RX_N11 LVDS or 2.5 V AD1

125 LVDS TX or CMOS I/O bit 12 DA5 HSMA_TX_P12 LVDS or 2.5 V AA7

126 LVDS RX or CMOS I/O bit 12 DB5 HSMA_RX_P12 LVDS or 2.5 V AB2

127 LVDS TX or CMOS I/O bit 12 DA4 HSMA_TX_N12 LVDS or 2.5 V AA6

128 LVDS RX or CMOS I/O bit 12 DB4 HSMA_RX_N12 LVDS or 2.5 V AC1

131 LVDS TX or CMOS I/O bit 13 DA3 HSMA_TX_P13 LVDS or 2.5 V Y8

132 LVDS RX or CMOS I/O bit 13 DB3 HSMA_RX_P13

LVDS or 2.5 V AA1

133 LVDS TX or CMOS I/O bit 13 DA2 HSMA_TX_N13 LVDS or 2.5 V Y7

134 LVDS RX or CMOS I/O bit 13 DB2 HSMA_RX_N13 LVDS or 2.5 V AB1

137 LVDS TX or CMOS I/O bit 14 DA1 HSMA_TX_P14 LVDS or 2.5 V Y10

Table B–1. HSMC Port A Interface Pin-Out Information (Part 2 of 3)

Data Conversion HSMC Schematic Development Board Schematic

Board

Reference

(J1) Description

Schematic

Signal Name

Schematic

Signal Name I/O Standard

Stratix III

Number

1 2 ... 29 30 31 32 33 34 35 36 37 38 39 ... 43 44

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