Altera Data Conversion HSMC Bedienungsanleitung PDF herunterladen (Seite 32)

A–8 Appendix A: Pin-Out Information for the Cyclone III (3C120)

Development Board

Data Conversion HSMC Reference Manual © November 2008 Altera Corporation

131 LVDS TX 13p or CMOS I/O data bit 60 DA3 HSMB_TX_D_P13 LVDS or

2.5 V

Y23

132 LVDS RX 13p or CMOS I/O data bit 61 DB3 HSMB_RX_D_P13 LVDS or

2.5 V

W28

133 LVDS TX 13n or CMOS I/O data bit 62 DA2 HSMB_TX_D_N13 LVDS or

2.5 V

Y24

134 LVDS RX 13n or CMOS I/O data bit 63 DB2 HSMB_RX_D_N13 LVDS or

2.5 V

W27

137 LVDS TX 14p or CMOS I/O data bit 64 DA1 HSMB_TX_D_P14 LVDS or

2.5 V

AE27

138 LVDS TX 14p or CMOS I/O data bit 65 DB1 HSMB_RX_D_P14 LVDS or

2.5 V

V23

139 LVDS RX 14n or CMOS I/O data bit 66 DA0 HSMB_TX_D_N14 LVDS or

2.5 V

AE28

140 LVDS RX 14n or CMOS I/O data bit 67 DB0 HSMB_RX_D_N14 LVDS or

2.5 V

V24

143 LVDS RX 15p or CMOS I/O data bit 68 AIC_DIN HSMB_TX_D_P15 LVDS or

2.5 V

W22

144 LVDS TX 15p or CMOS I/O data bit 69 AIC_DOUT HSMB_RX_D_P15 LVDS or

2.5 V

AB27

145 LVDS RX 15n or CMOS I/O data bit 70 AIC_LRCIN HSMB_TX_D_N15 LVDS or

2.5 V

Y22

146 LVDS RX 15n or CMOS I/O data bit 70 AIC_LRCOUT HSMB_RX_D_N15 LVDS or

2.5 V

AB28

149 LVDS RX 16p or CMOS I/O data bit 72 AIC_BCLK HSMB_TX_D_P16 LVDS or

2.5 V

V21

150 LVDS TX 16p or CMOS I/O data bit 73 AIC_XCLK HSMB_RX_D_P16 LVDS or

2.5 V

AC27

151 LVDS TX 16n or CMOS I/O data bit 74 AIC_SPI_CS HSMB_TX_D_N16 LVDS or

2.5 V

W21

155 LVDS or CMOS clock out FPGA_CLK_B_P HSMB_CLK_OUT_P2 LVDS AD27

156 LVDS or CMOS clock in ADA_DCO HSMB_CLK_IN_P2 LVDS Y27

157 LVDS or CMOS clock out FPGA_CLK_B_N HSMB_CLK_OUT_N2 2.5 V AD28

158 LVDS or CMOS clock in ADB_DCO HSMB_CLK_IN_N2 2.5 V Y28

Table A–2. HSMC Port B Interface Pin-Out Information (Part 4 of 4)

Data Conversion HSMC Schematic Development Board Schematic

Board

Reference

(J1) Description

Schematic

Signal Name

Schematic

Signal Name

I/O

Standard

Cyclone

III

Number

1 2 ... 27 28 29 30 31 32 33 34 35 36 37 ... 43 44

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