Altera Cyclone V GT FPGA Development Board Bedienungsanleitung PDF herunterladen (Seite 53)

Chapter 2: Board Components 2–45

Memory

September 2014 Altera Corporation Cyclone V GT FPGA Development Board

Reference Manual

DDR3B_RESETN

AG31 1.5-V SSTL Class I Reset

DDR3B_WEN

AM34 1.5-V SSTL Class I Write enable

DDR3B_ZQ2

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U8)

DDR3B_A0

H29 1.5-V SSTL Class I Address bus

DDR3B_A1

K28 1.5-V SSTL Class I Address bus

DDR3B_A2

K34 1.5-V SSTL Class I Address bus

DDR3B_A3

L32 1.5-V SSTL Class I Address bus

DDR3B_A4

R32 1.5-V SSTL Class I Address bus

DDR3B_A5

R33 1.5-V SSTL Class I Address bus

DDR3B_A6

N32 1.5-V SSTL Class I Address bus

DDR3B_A7

G33 1.5-V SSTL Class I Address bus

DDR3B_A8

AE34 1.5-V SSTL Class I Address bus

DDR3B_A9

L27 1.5-V SSTL Class I Address bus

DDR3B_A10

V33 1.5-V SSTL Class I Address bus

DDR3B_A11

U33 1.5-V SSTL Class I Address bus

DDR3B_A12

T31 1.5-V SSTL Class I Address bus

DDR3B_A13

T30 1.5-V SSTL Class I Address bus

DDR3B_BA0

J31 1.5-V SSTL Class I Bank address bus

DDR3B_BA1

N29 1.5-V SSTL Class I Bank address bus

DDR3B_BA2

P27 1.5-V SSTL Class I Bank address bus

DDR3B_CASN

N27 1.5-V SSTL Class I Row address select

DDR3B_CKE

AF32 1.5-V SSTL Class I Column address select

DDR3B_CLK_P

R30

Differential 1.5-V SSTL

Class I

Differential output clock

DDR3B_CLK_N

R29

Differential 1.5-V SSTL

Class I

Differential output clock

DDR3B_CSN

V27 1.5-V SSTL Class I Chip select

DDR3B_DM4

M33 1.5-V SSTL Class I Write mask byte lane

DDR3B_DM5

K32 1.5-V SSTL Class I Write mask byte lane

DDR3B_DQ32

T32 1.5-V SSTL Class I Data bus byte lane 4

DDR3B_DQ33

N33 1.5-V SSTL Class I Data bus byte lane 4

DDR3B_DQ34

T33 1.5-V SSTL Class I Data bus byte lane 4

DDR3B_DQ35

L33 1.5-V SSTL Class I Data bus byte lane 4

DDR3B_DQ36

T28 1.5-V SSTL Class I Data bus byte lane 4

DDR3B_DQ37

J34 1.5-V SSTL Class I Data bus byte lane 4

DDR3B_DQ38

T27 1.5-V SSTL Class I Data bus byte lane 4

DDR3B_DQ39

M34 1.5-V SSTL Class I Data bus byte lane 4

DDR3B_DQ40

K33 1.5-V SSTL Class I Data bus byte lane 5

Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 6)

Board Reference

Schematic

Signal Name

Cyclone V GT

Pin Number

I/O Standard Description

1 2 ... 48 49 50 51 52 53 54 55 56 57 58 ... 65 66

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