Altera Cyclone V GT FPGA Development Board Bedienungsanleitung PDF herunterladen (Seite 46)

2–38 Chapter 2: Board Components

Memory

Cyclone V GT FPGA Development Board September 2014 Altera Corporation

Reference Manual

DDR3A_A6

AK17 1.5-V SSTL Class I Address bus

DDR3A_A7

AL17 1.5-V SSTL Class I Address bus

DDR3A_A8

AH16 1.5-V SSTL Class I Address bus

DDR3A_A9

AJ16 1.5-V SSTL Class I Address bus

DDR3A_A10

AL16 1.5-V SSTL Class I Address bus

DDR3A_A11

AM16 1.5-V SSTL Class I Address bus

DDR3A_A12

AM13 1.5-V SSTL Class I Address bus

DDR3A_A13

AN13 1.5-V SSTL Class I Address bus

DDR3A_BA0

AN16 1.5-V SSTL Class I Bank address bus

DDR3A_BA1

AN17 1.5-V SSTL Class I Bank address bus

DDR3A_BA2

AP17 1.5-V SSTL Class I Bank address bus

DDR3A_CASN

AP15 1.5-V SSTL Class I Row address select

DDR3A_CKE

AP26 1.5-V SSTL Class I Column address select

DDR3A_CLK_P

AA18

Differential 1.5-V SSTL

Class I

Differential output clock

DDR3A_CLK_N

AA17

Differential 1.5-V SSTL

Class I

Differential output clock

DDR3A_CSN

AA16 1.5-V SSTL Class I Chip select

DDR3A_DM0

AL21 1.5-V SSTL Class I Write mask byte lane

DDR3A_DM1

AM24 1.5-V SSTL Class I Write mask byte lane

DDR3A_DQ0

AN19 1.5-V SSTL Class I Data bus byte lane 0

DDR3A_DQ1

AM19 1.5-V SSTL Class I Data bus byte lane 0

DDR3A_DQ2

AP20 1.5-V SSTL Class I Data bus byte lane 0

DDR3A_DQ3

AP21 1.5-V SSTL Class I Data bus byte lane 0

DDR3A_DQ4

AH19 1.5-V SSTL Class I Data bus byte lane 0

DDR3A_DQ5

AG19 1.5-V SSTL Class I Data bus byte lane 0

DDR3A_DQ6

AJ19 1.5-V SSTL Class I Data bus byte lane 0

DDR3A_DQ7

AM21 1.5-V SSTL Class I Data bus byte lane 0

DDR3A_DQ8

AM20 1.5-V SSTL Class I Data bus byte lane 1

DDR3A_DQ9

AL20 1.5-V SSTL Class I Data bus byte lane 1

DDR3A_DQ10

AN22 1.5-V SSTL Class I Data bus byte lane 1

DDR3A_DQ11

AN23 1.5-V SSTL Class I Data bus byte lane 1

DDR3A_DQ12

AP24 1.5-V SSTL Class I Data bus byte lane 1

DDR3A_DQ13

AP25 1.5-V SSTL Class I Data bus byte lane 1

DDR3A_DQ14

AN26 1.5-V SSTL Class I Data bus byte lane 1

DDR3A_DQ15

AN24 1.5-V SSTL Class I Data bus byte lane 1

DDR3A_DQS_P0

AB19

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 0

DDR3A_DQS_N0

AC19

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 0

Table 2–28. DDR3A Device Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5)

Board Reference

Schematic

Signal Name

Cyclone V GT

Pin Number

I/O Standard Description

1 2 ... 41 42 43 44 45 46 47 48 49 50 51 ... 65 66

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