Altera Cyclone IV GX FPGA Development Board Bedienungsanleitung PDF herunterladen (Seite 41)

Chapter 2: Board Components 2–33

Components and Transceiver Interfaces

May 2013 Altera Corporation Cyclone IV GX FPGA Development Board

Reference Manual

Table 2–34 lists the HSMC port B interface pin assignments, signal names, and

functions.

J1.150 LVDS RX bit 16 or CMOS bit 73

HSMA_RX_D_P16

LVDS or 2.5-V or

1.8-V

U21

J1.151 LVDS TX bit 16n or CMOS bit 74

HSMA_TX_D_N16

M22

J1.152 LVDS RX bit 16n or CMOS bit 75

HSMA_RX_D_N16

T21

J1.155 LVDS or CMOS clock out 2 or CMOS bit 76

HSMA_CLK_OUT_P2

K28

J1.156 LVDS or CMOS clock in 2 or CMOS bit 77

HSMA_CLK_IN_P2

V29

J1.157 LVDS or CMOS clock out 2 or CMOS bit 78

HSMA_CLK_OUT_N2

K29

J1.158 LVDS or CMOS clock in 2 or CMOS bit 79

HSMA_CLK_IN_N2

V30

J1.160 HSMC Port A presence detect

HSMA_PSNTn

2.5-V

A25

User LED to show RX data activity on

HSMC Port A

HSMA_RX_LED

C24

User LED to show TX data activity on

HSMC Port A

HSMA_TX_LED

D25

Table 2–33. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)

Board

Reference

Description

Schematic Signal

Name

I/O Standard

Cyclone IV GX

Device

Pin Number

Table 2–34. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 5)

Board

Reference

Description Schematic Signal

Name

I/O Standard

Cyclone IV GX

Device

Pin Number

Other

Connections

J2.17 Transceiver TX bit 3

HSMB_TX_P3

1.5-V

— C329.1

J2.18 Transceiver RX bit 3

HSMB_RX_P3

—R97.2

J2.19 Transceiver TX bit 3n

HSMB_TX_N3

— C346.1

J2.20 Transceiver RX bit 3n

HSMB_RX_N3

— R101.2

J2.21 Transceiver TX bit 2

HSMB_TX_P2

— C327.1

J2.22 Transceiver RX bit 2

HSMB_RX_P2

—R94.2

J2.23 Transceiver TX bit 2n

HSMB_TX_N2

— C344.1

J2.24 Transceiver RX bit 2n

HSMB_RX_N2

—R95.2

J2.25 Transceiver TX bit 1

HSMB_TX_P1

— C325.1

J2.26 Transceiver RX bit 1

HSMB_RX_P1

—R89.2

J2.27 Transceiver TX bit 1n

HSMB_TX_N1

— C342.1

J2.28 Transceiver RX bit 1n

HSMB_RX_N1

—R91.2

J2.29 Transceiver TX bit 0

HSMB_TX_P0

— C323.1

J2.30 Transceiver RX bit 0

HSMB_RX_P0

—R86.2

J2.31 Transceiver TX bit 0n

HSMB_TX_N0

— C340.1

J2.32 Transceiver RX bit 0n

HSMB_RX_N0

—R87.2

J2.33 Management serial data

HSMB_T_SDA

2.5-V

—U39.1

J2.34 Management serial clock

HSMB_T_SCL

—U39.8

J2.37 JTAG data output

HSMB_JTAG_TDO

— U2.5

J2.38 JTAG data input

HSMB_JTAG_TDI

— U1.9; U2.2

1 2 ... 36 37 38 39 40 41 42 43 44 45 46 ... 59 60

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