Altera Arria V SoC Development Board Bedienungsanleitung PDF herunterladen (Seite 52)

2–44 Chapter 2: Board Components

Memory

Arria V SoC Development Board July 2014 Altera Corporation

Reference Manual

DDR3B_RESETN

AN15 1.5-V SSTL Class I Reset

DDR3B_WEN

AP18 1.5-V SSTL Class I Write enable

DDR3B_ZQ1

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U43)

DDR3B_A0

AP16 1.5-V SSTL Class I Address bus

DDR3B_A1

AN16 1.5-V SSTL Class I Address bus

DDR3B_A2

AK16 1.5-V SSTL Class I Address bus

DDR3B_A3

AJ16 1.5-V SSTL Class I Address bus

DDR3B_A4

AV16 1.5-V SSTL Class I Address bus

DDR3B_A5

AU16 1.5-V SSTL Class I Address bus

DDR3B_A6

AT16 1.5-V SSTL Class I Address bus

DDR3B_A7

AR16 1.5-V SSTL Class I Address bus

DDR3B_A8

AP17 1.5-V SSTL Class I Address bus

DDR3B_A9

AN17 1.5-V SSTL Class I Address bus

DDR3B_A10

AH17 1.5-V SSTL Class I Address bus

DDR3B_A11

AG17 1.5-V SSTL Class I Address bus

DDR3B_A12

AM18 1.5-V SSTL Class I Address bus

DDR3B_A13

AL18 1.5-V SSTL Class I Address bus

DDR3B_A14

AG18 1.5-V SSTL Class I Address bus

DDR3B_BA0

AE18 1.5-V SSTL Class I Bank address bus

DDR3B_BA1

AD18 1.5-V SSTL Class I Bank address bus

DDR3B_BA2

AC18 1.5-V SSTL Class I Bank address bus

DDR3B_CASN

AR18 1.5-V SSTL Class I Row address select

DDR3B_CKE

AM16 1.5-V SSTL Class I Column address select

DDR3B_CLK_P

AF16 1.5-V SSTL Class I Differential output clock

DDR3B_CLK_N

AE17 1.5-V SSTL Class I Differential output clock

DDR3B_CSN

AL17 1.5-V SSTL Class I Chip select

DDR3B_DM0

AD16 1.5-V SSTL Class I Write mask byte lane

DDR3B_DM1

AU13 1.5-V SSTL Class I Write mask byte lane

DDR3B_DQ0

AU15 1.5-V SSTL Class I Data bus

DDR3B_DQ1

AT15 1.5-V SSTL Class I Data bus

DDR3B_DQ2

AH15 1.5-V SSTL Class I Data bus

DDR3B_DQ3

AW13 1.5-V SSTL Class I Data bus

DDR3B_DQ4

AV13 1.5-V SSTL Class I Data bus

DDR3B_DQ5

AL15 1.5-V SSTL Class I Data bus

DDR3B_DQ6

AW15 1.5-V SSTL Class I Data bus

DDR3B_DQ7

AW14 1.5-V SSTL Class I Data bus

DDR3B_DQ8

AE15 1.5-V SSTL Class I Data bus

Table 2–27. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 6 of 7)

Board

Reference

Schematic

Signal Name

Arria V SoC Pin

Number

I/O Standard Description

1 2 ... 47 48 49 50 51 52 53 54 55 56 57 ... 69 70

Kommentare zu diesen Handbüchern

Keine Kommentare

Altera Arria V SoC Development Board Bedienungsanleitung Seite 52

Kommentare zu diesen Handbüchern

Verwandte Produkte und Handbücher für Messgeräte Altera Arria V SoC Development Board