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Altera Arria V Avalon-ST Handbücher

Bedienungsanleitungen und Benutzerhandbücher für Messgeräte Altera Arria V Avalon-ST.
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Altera Arria V Avalon-ST Bedienungsanleitung (248 Seiten)


Marke: Altera | Kategorie: Messgeräte | Größe: 2.09 MB |

 

Inhaltsverzeichnis

User Guide

1

Datasheet

2

Features

3

Release Information

5

Device Family Support

6

Altera FPGA

7

Arria V or Cyclone V FPGA

8

Debug Features

10

IP Core Verification

11

Recommended Speed Grades

11

Qsys Design Flow

15

Generating the Testbench

17

Simulating the Example Design

17

Directory Description

18

Modifying the Example Design

21

Parameter Settings

24

Parameter Value Description

25

Link Capabilities

27

Device Capabilities

28

Error Reporting

30

Slot Capabilities

31

Power Management

32

<n>

34

Legacy Interrupt

37

Application Layer

39

Avalon‑ST RX Interface

39

Signal Direction Description

40

Packet TLP

43

Aligned Addresses

47

Avalon-ST TX Interface

50

Clock Signals

61

Reset Signals

61

Hard IP Status

63

Error Signals

66

ECRC Forwarding

66

Interrupts for Endpoints

67

Completion Side Band Signals

68

Signal Directi

69

Description

69

Field and Bit Map

78

0134678951

78

LMI Signals

79

Hard IP for PCIe

80

Power Management Signals

82

15 011623 8 2791213142431

83

Bits Field Description

84

Serial Interface Signals

86

9 Ch 18 Ch

87

Variant Data CMU Clock

88

PIPE Interface Signals

91

Test Signals

95

Registers

100

Altera Corporation

100

Send Feedback

100

2014.12.15

101

Altera-Defined VSEC Registers

104

CvP Registers

105

Bits Register Description

109

Reset and Clocks

112

Example Design

113

Hard IP for PCI Express

113

Clock Domains

116

Data Rate Frequency

117

Related Information

117

Clock Summary

118

Interrupts

119

Figure 7-1: MSI Handler Block

120

Allocated

121

Implementing MSI-X Interrupts

122

Legacy Interrupts

124

Interrupts for Root Ports

125

Error Handling

126

Physical Layer Errors

127

Data Link Layer Errors

127

Transaction Layer Errors

128

Error Type Description

129

Status Bit Conditions

132

IP Core Architecture

134

Hard IP for PCI Express

135

Top-Level Interfaces

136

Avalon-ST Interface

136

Clocks and Reset

136

Hard IP Reconfiguration

137

Transceiver Reconfiguration

137

Transaction Layer

138

Configuration Space

139

Data Link Layer

140

Physical Layer

142

TX Packets

143

Multi-Function Support

144

Supported Message Types

146

INTX Messages

146

Power Management Messages

147

Error Signaling Messages

148

Locked Transaction Message

149

Slot Power Limit Message

149

Vendor-Defined Messages

149

Hot Plug Messages

150

Receive Buffer Reordering

152

Using Relaxed Ordering

154

Throughput Optimization

157

Throughput of Posted Writes

159

Design Implementation

161

Making Pin Assignments

162

Optional Features

163

ECRC on the RX Path

164

ECRC on the TX Path

165

Subscribe

168

Testbench and Design Example

171

Root Port Testbench

174

Chaining DMA Design Examples

174

Root Complex

176

Chaining DMA

176

Hard IP for

176

PCI Express

176

BAR/Address Map

179

Memory BAR Mapping

180

Bit Field Description

181

Addr Register Name

181

Byte Address

184

Offset to Base

184

Descriptor Type Description

184

Bits[21:18] Bit[17] Bit[16]

185

Descriptor Field Endpoint

185

RC Access Description

185

Test Driver Module

186

DMA Write Cycles

187

Shared Memory

188

DMA Read Cycles

189

Registers (BAR2)

190

Root Port Design Example

191

Root Port

192

Variation

192

(variation_name.v)

192

Root Port BFM

193

BFM Configuration Procedures

194

BFM Request Interface

194

BFM Memory Map

195

Offset (Bytes) Description

197

BFM Procedures and Functions

201

Location altpcietb_bfm_rdwr.v

202

Express address

203

Shared Memory Constants

210

Constant Description

211

Location

216

Debugging Simulations

228

Debugging

229

Setting Up Simulation

232

Use Third-Party PCIe Analyzer

234

BIOS Enumeration Issues

234

Address[31:2]

235

Figure A-6: I/O Read Request

237

7 6 5 4 3 2 1 0

241

Core Config 8 4 1

241

Additional Information

243

Date Version Changes Made

244

How to Contact Altera

246

Typographic Conventions

247

Visual Cue Meaning

248




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