Altera Active Serial Memory Interface Bedienungsanleitung PDF herunterladen (Seite 25)

operation. Therefore, the fast read operation performs faster than the read operation. The IP core

asserts the data_valid signal for one clock cycle, to indicate dataout[7..0] contains a new valid

data.

If you enable the read_address[23..0] signal in the IP parameter editor, the read address for

each data byte on dataout[7..0] signal appears on the read_address[23..0] signal.

Assert the rden signal until you have finished reading sequential data from the EPCS/EPCQ/

EPCQ-L device. This condition allows you to read every memory address from the EPCS/EPCQ/

EPCQ-L device with a single read command.

The data from the next address appears on the dataout[7..0] signal and its memory address

appears on the read_address[23..0] signal at every eight clkin clock cycles. The data_valid

signal is asserted for one clock cycle after the new data byte appears on the dataout[7..0] signal.

Use the data_valid signal as an indication to capture the new data byte.

When the second-to-last byte of data to be read appears on the dataout[7..0] signal, and the

data_valid is asserted, deassert the rden signal to indicate the end of the fast read command.

The final data byte appears on the dataout[7..0] signal, the data_valid is reasserted, and then

the IP core deasserts the busy signal.

For a single-byte fast read operation, assert the rden and the fast_read signals for a single clock

cycle, or deassert the rden at any time before the first data byte appears on the dataout[7..0]

signal, and the data_valid signal is asserted for the first time.

Monitor the data_valid signal to ensure you sample the dataout[7..0] signal only when the

data_valid signal is asserted.

After the fast read operation is complete, the dataout[7..0] signal holds the value of the last

byte read until you issue a new fast read command or reset the device.

Note:

The fast_read, rden, and addr[7..0] signals must adhere to setup and hold time

requirements for the clkin signal. These signals must remain stable at the rising

edge of the clkin signal.

Note: For EPCQ256/EPCQ_L256 or larger devices, the width of the addr and

read_address signals is 32 bit.

EPCQ/EPCQ-L Devices Extended SPI Dual and Quad I/O Instruction

Other than the standard SPI protocol, EPCQ/EPCQ-L devices also support fast read commands with

multiple I/O data transfer. For standard SPI instruction, DQ0 only sends data to the EPCQ/EPCQ-L while

DQ1 receives data from the EPCQ/EPCQ-L device. With multiple I/O, the instruction operation codes are

sent in DQ0 and the rest of data is transferred in multiple data lines; two data lines (DQ0, DQ1) for dual

I/O and four data lines (DQ0, DQ1, DQ2, DQ3) for quad I/O.

To use the fast read operation with multiple I/O, the command is the same as fast read operation with the

standard I/O. For the multiple-byte and single-byte operations, refer to Figure 8 and Figure 9. The

differences are handled in Altera ASMI Parallel IP core and you only need to use the operation as per

usual.

For EPCS/EPCQ/EPCQ-L devices, the IP core generates the first data byte on the dataout[7..0] port

after eight cycles and then it appears for the read command. The eight cycles are the dummy clock cycles

designated in Altera ASMI Parallel IP core in accordance to the default dummy clock value in the EPCS/

EPCQ/EPCQ-L datasheet. The EPCS/EPCQ/EPCQ-L standard I/O and EPCQ/EPCQ-L dual I/O have

default dummy clock value of 8, while EPCQ/EPCQ-L quad I/O has default dummy clock value of 10. So,

UG-ALT1005

2014.12.15

EPCQ/EPCQ-L Devices Extended SPI Dual and Quad I/O Instruction

Altera ASMI Parallel IP Core User Guide

Altera Corporation

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