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Altera Nios II Handbücher

Bedienungsanleitungen und Benutzerhandbücher für Prozessoren Altera Nios II.
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Altera Nios II Bedienungsanleitung (38 Seiten)


Marke: Altera | Kategorie: Prozessoren | Größe: 1.21 MB |

 

Inhaltsverzeichnis

Altera Nios II

1

Table of Contents

2

1 Introduction

3

1.1 About QP™

4

1.3 Licensing QP™

5

2 Installation

6

3.1 Launching the Nios II IDE

8

3.2 Configuring the FPGA

10

3.3 Debugging the Application

12

11 of 36

13

3.5 Configuring the BSP

19

3.7.1 Building the QS library

21

4 The Vanilla QP Port

26

4.2.2 The Time-Tick Interrupt

27

5 The QK Port

30

NOTE: The idle callback

33

8 Contact Information

38

Altera Nios II Bedienungsanleitung (85 Seiten)


Marke: Altera | Kategorie: Prozessoren | Größe: 5.32 MB |

 

Inhaltsverzeichnis

My First Nios II for

1

Altera DE2i-150 Board

1

CONTENTS

2

Hardware Design

3

Figure 1-9 Qsys Menu

12

Figure 1-11 Save System

14

Figure 1-12 Rename System

15

Figure 1-13 A New System

15

Figure 1-17

17

Figure 1-22 JTAG UART (2)

21

Figure 1-23 JTAG UART

22

Figure 1-24 Rename JTAG UAR

22

Figure 1-37 Add PIO

34

Figure 1-38 Add PIO

35

Figure 1-39 PIO

36

Figure 1-40 Rename PIO

36

Figure 1-44 No Errors

38

Figure 1-47 Generate Qsys

40

Figure 1-48 Generate Qsys

40

Figure 1-50

41

Figure 1-50 Exit Qsys

41

Figure 1-51 New Verilog file

42

Figure 1-52 New Verilog File

43

Figure 1-59 Add file

48

Figure 1-60 Add file

48

Figure 1-65 Pins menu

52

Figure 1-66 Blank Pins

52

Figure 1-67 Set Pins

52

(SBT) for Eclipse

53

NIOS II Softwar Build

56

Tools for Eclipse

56

Figure 2-9 Configuring BSP

66

Programming the CFI Flash

67

Program Flash

84

Altera Nios II Spezifikationen (468 Seiten)


Marke: Altera | Kategorie: Prozessoren | Größe: 2.66 MB |

 

Inhaltsverzeichnis

Handbook

1

Contents

2

Altera Corporation

10

Finding Nios II EDS Files

13

Nios II EDS Development Flows

14

Nios II Programs

15

Application Project

16

User Library Project

16

BSP Project

16

Hardware Examples

17

Software Examples

17

Development

19

Interface

21

Creating a Project

22

Specifying the BSP

23

Navigating the Project

24

Building the Project

24

Configuring the FPGA

24

Creating a Simple BSP

31

Eclipse Source Management

32

User Source Management

33

Using the BSP Editor

34

The Command Area

35

The Software Packages Tab

36

The Drivers Tab

36

The Linker Script Tab

37

The Console Area

38

Exporting a Tcl Script

39

Creating a New BSP

39

BSP Validation Errors

40

The Project Tab

41

The Target Connection Tab

41

The Debugger Tab

41

Nios II Hardware v2 (beta)

42

Optimizing Project Build Time

42

Nios II Command-Line Projects

43

Road Map

43

Import a Supporting Project

44

Packaging a Library for Reuse

45

Creating a Software Package

46

Starting the Flash Programmer

48

Flash Programmer Options

50

Program Files

51

Potential Error Message

54

Nios II GCC Tool Chain

54

Eclipse Usage Notes

56

Target Connection Options

57

Renaming Nios II Projects

57

CDT Limitations

58

Build Configurations in SBT

60

Utilities

64

Command Summary

65

Tcl Commands

67

Tcl Scripts

67

Prerequisites

68

Debugging hello_world

70

Creating a BSP with a Script

72

Argument Purpose

74

Running make

75

Road Map for the SBT

78

Makefiles

78

Modifying Makefiles

79

Makefile Targets

79

Applications and Libraries

80

Board Support Packages

81

Common BSP Tasks

83

Using Version Control

84

Linking and Locating

86

Target Operation

87

Other BSP Tasks

91

Querying Settings

92

Managing Device Drivers

92

Controlling the stdio Device

93

Details of BSP Creation

95

BSP Settings File Creation

97

Generated and Copied Files

97

HAL BSP Files and Folders

97

File Name Function

98

Copied BSP Files

100

HAL BSP After Build

101

Tcl Scripts for BSP Settings

102

Simple Tcl Script

103

2015.05.14

104

Revising Your BSP

105

Regenerating Your BSP

106

How to Regenerate Your BSP

107

Updating Your BSP

108

Recreating Your BSP

109

Specifying BSP Defaults

110

Script Level Summary

111

Related Information

111

Argument Name Argument Value

112

Memory Types

115

Boot from Flash Configuration

116

The Nios II SBT for Eclipse

118

The Nios II Command Shell

119

GNU Compiler Tool Chain

120

Nios II Software Build Tools

121

File Format Conversion Tools

121

Other Command-Line Tools

122

Restrictions

123

Date Version Changes

124

Subscribe

125

Send Feedback

125

Services

126

Layers of a HAL-Based System

126

Applications versus Drivers

126

Generic Device Models

127

C Standard Library—newlib

128

Supported Peripherals

128

Provide Partial HAL Support

129

MPU Support

130

MMU Support

130

Abstraction Layer

132

UNIX-Style Interface

135

File System

136

Using Character-Mode Devices

137

C++ Streams

138

/dev/null

138

Altera Logging Functions

138

Enabling Altera Logging

139

Extra Logging Options

140

Name Description

141

Logging Levels

142

Custom Logging Messages

143

Altera Logging Files

143

Using File Subsystems

144

Using Timer Devices

145

Timestamp Driver

147

Using Flash Devices

148

Simple Flash Access

149

Block Erasure or Corruption

149

Fine-Grained Flash Access

150

Using DMA Devices

154

DMA Transmit Channels

155

DMA Receive Channels

155

Using Interrupt Controllers

158

Enable Compiler Optimizations

159

Use Reduced Device Drivers

159

Use /dev/null

159

Limitation Functions Affected

160

Use UNIX-Style File I/O

162

Emulate ANSI C Functions

162

Eliminate Unneeded Exit Code

164

Boot Sequence and Entry Point

165

Customizing the Boot Sequence

166

Memory Usage

167

Simple Placement Options

168

Advanced Placement Options

169

Global Pointer Register

170

Working with HAL Source Files

172

Hardware Abstraction Layer

173

Accessing Hardware

177

Character-Mode Device Drivers

179

Function Default Behavior

180

File Subsystem Drivers

181

Timer Device Drivers

182

Flash Device Drivers

183

DMA Device Drivers

184

Ethernet Device Drivers

185

Hardware

186

Software

186

Overview

189

Assumptions and Requirements

190

The Nios II BSP Generator

191

File Names and Locations

192

Data Type Setting Value Notes

199

Device Driver Source Code

203

Using Macros

204

HAL Namespace Allocation

205

Exception Handling

208

Interrupt Controllers

210

Latency and Response Time

212

Selecting an Interrupt API

214

Function Name Implemented By

215

The Legacy HAL Interrupt API

216

HAL ISR Restrictions

218

Writing an ISR

218

Managing Pre-Emption

219

C Example

222

Increase Buffer Size

225

Use Double Buffering

225

Keep Interrupts Enabled

225

Use Fast Memory

225

Use Compiler Optimization

229

Add Fast Memory

230

Debugging Nios II ISRs

231

General Exception Funnel

233

Hardware Interrupt Funnel

233

Software Exception Funnel

235

Unimplemented Instructions

236

Software Trap Handling

238

Miscellaneous Exceptions

238

Invalid Instructions

239

Exception Cause Codes

240

Exception Cause

241

Cause Symbol

241

Nios II Cache Implementation

244

Defining Cache Properties

245

For HAL Users

246

For Users of the HAL

248

Bit-31 Cache Bypass

248

Further Information

251

Other RTOS Providers

252

MicroC/OS-II Device Drivers

253

Thread-Safe HAL Drivers

254

Macro Defined in

255

HAL Implementa‐

255

Nios II Edition

258

Licensing

260

Nios II System Requirements

260

Initializing the Stack

261

Calling the Sockets Interface

264

Option Description

265

Known Limitations

267

- Nios II Edition

267

Read-Only Zip File System

268

Embedded Software

270

Embedded Software Assignments

271

Configuration Namespace

272

Configuration Data Types

273

Streaming Source Information

276

Streaming Sink Information

277

HAL API Reference

280

_rename()

281

Request Meaning

304

HAL Standard Types

354

Setting Values

360

Utility and Script Summary

360

Example BSP

381

Application Name Summary

381

Overview of BSP Settings

384

Setting Context Description

385

Settings Reference

386

Standard Build Flag Variables

421

Tcl Command Environments

422

Tcl Commands for BSP Settings

422

Command Arguments

465

Object File Directory Tree

466

Altera Nios II Spezifikationen (269 Seiten)


Marke: Altera | Kategorie: Prozessoren | Größe: 2.37 MB |

 

Inhaltsverzeichnis

101 Innovation Drive

1

San Jose, CA 95134

1

Contents

2

Altera Corporation

10

Introduction

10

Send Feedback

10

Related Information

11

Standard Peripherals

12

OpenCore Plus Evaluation

13

Processor Architecture

16

Processor Implementation

17

Register File

18

Floating-Point Instructions

20

Operation

23

Inference

23

Reset and Debug Signals

25

Exception Controller

26

EIC Interface

26

Memory and I/O Organization

27

Instruction and Data Buses

29

Memory and Peripheral Access

30

Instruction Master Port

30

Data Master Port

30

Cache Memory

31

Address Map

33

Download and Execute Software

36

Software Breakpoints

36

Hardware Breakpoints

36

Hardware Triggers

36

Trace Capture

37

Programming Model

40

Memory Management

42

Memory Protection

43

Virtual Memory Address Space

43

TLB Organization

44

Field Name Description

45

Memory Regions

47

Registers

48

General-Purpose Registers

49

NII51003

51

The status Register

52

The estatus Register

54

The bstatus Register

55

The ienable Register

55

The ipending Register

56

The cpuid Register

56

The exception Register

56

The pteaddr Register

57

The tlbacc Register

57

The tlbmisc Register

58

The badaddr Register

61

The config Register

62

The mpubase Register

63

The mpuacc Register

64

MASK Encoding Region Size

65

The sstatus Register

69

Working with the MPU

71

MPU Initialization

72

Debugger Access

72

Working with ECC

73

Instruction Cache Tag RAM

74

Instruction Cache Data RAM

74

Register File RAM Blocks

74

MMU TLB RAM

74

Exception Processing

75

Exception Latency

78

Reset Exceptions

78

Break Exceptions

79

Interrupt Exceptions

80

Internal Interrupt Controller

82

Trap Instruction

84

Break Instruction

84

Unimplemented Instruction

84

Illegal Instruction

84

Supervisor-Only Instruction

85

Supervisor-Only Data Address

85

Misaligned Data Address

85

Division Error

86

Fast TLB Miss

86

Double TLB Miss

87

TLB Permission Violation

87

MPU Region Violation

87

Other Exceptions

88

Exception Processing Flow

88

Handling Nested Exceptions

93

Disabling Maskable Interrupts

95

Virtual Address Aliasing

98

Instruction Set Categories

99

Move Instructions

100

Comparison Instructions

101

Shift and Rotate Instructions

101

Program Control Instructions

102

Other Control Instructions

103

Custom Instructions

104

No-Operation Instruction

104

Document Revision History

105

September 2004 1.1

106

May 2004 1.0 Initial release

106

Core Nios II Tab

107

Core Selection

108

Multiply and Divide Settings

109

Reset Vector

109

General Exception Vector

110

Name Description

111

Instruction Master Settings

112

Advanced Features Tab

113

Reset Signals

114

Control Registers

114

Exception Checking

115

Shadow Register Sets

116

HardCopy Compatible

116

MMU and MPU Settings Tab

117

JTAG Debug Module Tab

119

Debug Level Settings

120

Debug Signals

121

Break Vector

121

Custom Instruction Tab

122

The Quartus II IP File

124

Date Version Changes

126

2015.04.02

127

NII51015

128

Device Family Support

129

Nios II/f Core

129

Overview

130

Arithmetic Logic Unit

130

Instruction

131

Result Latency

131

Supported Instructions

131

Memory Access

132

Instruction Cache

133

Tightly-Coupled Memory

135

Memory Management Unit

135

Memory Protection Unit

136

Execution Pipeline

136

Instruction Performance

137

Exception Handling

138

Nios II/s Core

141

Nios II/e Core

146

Instruction Execution Stages

147

JTAG Debug Module

148

Nios II Versions

150

Version Release Date Notes

151

Architecture Revisions

152

Core Revisions

153

JTAG Debug Module Revisions

157

Application Binary Interface

160

Memory Alignment

161

Register Usage

161

NII51016

162

Frame Pointer Elimination

163

Call Saved Registers

163

Further Examples of Stacks

164

Function Prologues

165

Arguments and Return Values

166

Return Values

167

DWARF-2 Definition

168

Object Files

168

Relocation

168

ABI for Linux Systems

171

Relocation Operator

172

Copy Relocation

173

Jump Slot Relocation

173

Thread-Local Storage

173

Linux Function Calls

175

Linux Process Initialization

176

Global Offset Table

179

Function Addresses

179

Procedure Linkage Table

179

Linux Conventions

181

Instruction Set Reference

184

Instruction Opcodes

185

NII51017

186

Assembler Pseudo-Instructions

187

Assembler Macros

188

Notation Meaning

189

Altera Nios II Spezifikationen (42 Seiten)


Marke: Altera | Kategorie: Prozessoren | Größe: 1.48 MB |

 

Inhaltsverzeichnis

Tutorial

1

Nios II Hardware Development

1

Contents

3

Design Example

5

Nios II System

6

Altera FPGA

6

Target Board

6

OpenCore Plus Evaluation

7

Analyzing System Requirements

9

Varying the Development Flow

11

Creating the Design Example

12

Analyze System Requirements

13

Create a New Qsys System

14

Define the System in Qsys

15

Add the On-Chip Memory

16

Add the JTAG UART

21

Add the Interval Timer

22

Add the System ID Peripheral

23

Add the PIO

24

Generate the Qsys System

27

Add IP Variation File

30

Compile the Project

38

Taking the Next Step

40

Note to Table:

41

Typographic Conventions

42

Altera Nios II Spezifikationen (232 Seiten)


Marke: Altera | Kategorie: Prozessoren | Größe: 1.92 MB |

 

Inhaltsverzeichnis

101 Innovation Drive

1

San Jose, CA 95134

1

Contents

3

Chapter 3. Programming Model

4

Section II. Appendices

5

Altera Corporation vii

7

Chapter Revision Dates

9

About This Handbook

11

How to Find

12

Further

12

Information

12

How to Contact

12

Typographical

13

Conventions

13

Typographical Conventions

14

Section I. Nios II

15

Processor

15

1. Introduction

17

Getting Started

18

Customizing

19

Nios II

19

Configurable

20

Soft-Core

20

Concepts

20

Standard Peripherals

21

Custom Peripherals

21

OpenCore Plus

22

Evaluation

22

1–8 Altera Corporation

24

Document Revision History

24

2. Processor Architecture

25

Implementation

26

Register File

27

Arithmetic Logic

28

Floating Point Instructions

29

Reset Signals

30

Exception and

30

Interrupt

30

Controller

30

ALT_CI_EXCEPTION_VECTOR_N

31

Memory and I/O

32

Organization

32

Instruction and Data Buses

33

Memory and Peripheral Access

34

Instruction Master Port

34

Data Master Port

35

Effective Use of Cache Memory

36

Cache Bypass Methods

37

Address Map

38

Download and Execute Software

40

Software Breakpoints

40

Hardware Breakpoints

40

Hardware Triggers

40

Armed Triggers

41

Execution vs. Data Trace

42

Trace Frames

43

3. Programming Model

45

Control

46

Registers

46

Operating

48

Exception

49

Processing

49

Reset Exceptions

50

Processing a Break

51

Returning From a Break

52

Altera Corporation 3–9

53

Programming Model

53

Trap Instruction

54

Break Instruction

54

Unimplemented Instruction

54

Other Exceptions

55

Exceptions

56

Nested Exception Precautions

57

Return Address Considerations

57

Memory and

58

Peripheral

58

Categories

59

Move Instructions

61

Comparison Instructions

61

Shift and Rotate Instructions

62

Program Control Instructions

63

Other Control Instructions

64

4. Instantiating the Nios II

67

Processor in SOPC Builder

67

Core Nios II

68

Core Selection

69

Multiply and Divide Settings

69

Reset Vector

70

Exception Vector

70

Altera Corporation 4–5

71

Caches and

72

Interfaces Page

72

Instruction Master Settings

73

Data Master Settings

74

Advanced

75

Features Page

75

Module Page

76

Feature Description

77

Debug Level Settings

78

Break Vector

79

Instructions

80

Altera Corporation 4–15

81

4–16 Altera Corporation

82

Custom Instructions Page

82

Altera Corporation 4–17

83

4–18 Altera Corporation

84

5. Nios II Core

89

Implementation Details

89

Feature Core

90

Nios II/e Nios II/s Nios II/f

90

Device Family

91

Nios II/f Core

91

Overview

92

Instruction and Data Caches

94

31... ...210

95

Bursting

96

Nios II/s Core

100

Arithmetic Logic Unit

101

Shift and Rotate Performance

102

Instruction Cache

103

Execution Pipeline

104

Pipeline Stalls

105

Branch Prediction

105

Exception Handling

106

JTAG Debug Module

106

Unsupported Features

106

Nios II/e Core

107

Instruction Execution Stages

108

Instruction Performance

108

Referenced

109

Documents

109

Document

110

Revision History

110

6. Nios II Processor Revision

111

Architecture

112

Revisions

112

Core Revisions

113

Version Release Date Notes

114

JTAG Debug

116

7. Application Binary

119

Interface

119

Alignment

120

Register Usage

120

Frame Pointer Elimination

122

Call Saved Registers

122

Further Examples of Stacks

123

Function Prologs

124

Prolog Variations

125

Arguments and

126

Return Values

126

8. Instruction Set Reference

129

Instruction

132

Altera Corporation 8–5

133

Instruction Set Reference

133

Assembler

134

Instruction Set

136

Reference

136

31..28

155

Altera Nios II Betriebsanweisung (37 Seiten)


Marke: Altera | Kategorie: Prozessoren | Größe: 0.66 MB |

 

Inhaltsverzeichnis

Nios II Flash Programmer

1

User Guide

1

Contents

3

Programmer

5

Prerequisites

6

Notes to Table 1–1:

7

Introduction

9

■ An arbitrary binary file

13

Command Line

15

from the beginning of flash

16

Notes to Table 3–2:

18

Note to Table 3–3:

19

Name Required Description

20

General Parameters

20

■ The processor's

21

■ The executable

21

--output=myapp.flash

22

Flash Override Files

25

Width Mode Override Parameter

26

C. Stand-Alone Mode

29

D. Troubleshooting

31

Probable Cause

32

Suggested Actions

32

Additional Information

35

How to Contact Altera

36

Typographic Conventions

36

Additional Information Info–3

37
Stratix GX Betriebsanweisung   Altera Stratix GX User guide, 318 Seiten

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