Altera Transceiver Signal Integrity Development Kit, Stra Bedienungsanleitung PDF herunterladen (Seite 42)

2–34 Chapter 2: Board Components

Components and Interfaces

Transceiver Signal Integrity Development Kit July 2012 Altera Corporation

Stratix V GX Edition Reference Manual

ENET_LED_LINK1000

2.5-V — 1000-Mb link LED

ENET_LED_RX

2.5-V — RX data active LED

ENET_LED_TX

2.5-V — TX data active LED

ENET_RSTN

2.5-V AT6 Device reset

ENET_SGMII_RX_N

2.5-V AJ15 SGMII receive

ENET_SGMII_RX_P

2.5-V AH15 SGMII receive

ENET_SGMII_TX_N

2.5-V AL15 SGMII transmit

ENET_SGMII_TX_P

2.5-V AK15 SGMII transmit

ENET_XTAL_25MHZ

2.5-V — 25-MHz clock

GTXCLK

2.5-V AE15 Ethernet transmit clock

MDC

2.5-V AB16 Management bus data clock

MDI_N0

2.5-V — Management bus data

MDI_N1

2.5-V — Management bus data

MDI_N2

2.5-V — Management bus data

MDI_N3

2.5-V — Management bus data

MDI_P0

2.5-V — Management bus data

MDI_P1

2.5-V — Management bus data

MDI_P2

2.5-V — Management bus data

MDI_P3

2.5-V — Management bus data

MDIO

2.5-V AC16 Management bus data input/output

RXCLK

2.5-V AH16 SGMII receive clock

RXD0

2.5-V AG17 SGMII receive data

RXD1

2.5-V AD15 SGMII receive data

RXD2

2.5-V AE16 SGMII receive data

RXD3

2.5-V AB15 SGMII receive data

RXDV

2.5-V AF17 SGMII receive data valid

TXD0

2.5-V AK17 SGMII transmit data

TXD1

2.5-V AL17 SGMII transmit data

TXD2

2.5-V AJ16 SGMII transmit data

TXD3

2.5-V AJ17 SGMII transmit data

TXEN

2.5-V AF16 SGMII transmit enable

Table 2–32. Ethernet PHY Pin Assignments, Signal Names and Functions

Board

Reference

(U22)

Schematic Signal Name I/O Standard

Stratix V GX Device

Pin Number

Description

1 2 ... 37 38 39 40 41 42 43 44 45 46 47 ... 57 58

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