Altera Quartus II Scripting Bedienungsanleitung PDF herunterladen (Seite 434)

100

101

3–304 Chapter 3: Tcl Packages & Commands

sdc

reset_design

Usage

reset_design

Options

None

Description

Removes all assignments from the design. This includes clocks, generated clocks, derived clocks, input

delays, output delays, clock latency, clock uncertainty, clock groups, false paths, multicycle paths, min

delays, and max delays. After reset_design is called, the design should be in the same state as it would be

if create_timing_netlist was just called.

Example

# Constrain design

create_clock -name clk -period 4.000 -waveform { 0.000 2.000 } \

[get_ports clk]

set_input_delay -clock clk2 1.5 [get_ports in*]

set_output_delay -clock clk 1.6 [get_ports out*]

set_false_path -from [get_keepers in] -through [get_nets r1] -to \

[get_keepers out]

# Reset the design to the state that it was in before any constraints

# were entered

reset_design

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