Altera DSP Development Kit, Stratix V Edition Bedienungsanleitung Seite 22

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2–14 Chapter 2: Board Components
Configuration, Status, and Setup Elements
DSP Development Kit, Stratix V Edition July 2012 Altera Corporation
Reference Manual
JTAG Chain
The on-board USB-Blaster II is automatically disabled when you connect an external
USB-Blaster to the JTAG chain or when you enable JTAG from the PCI Express edge
connector. Figure 2–3 illustrates the JTAG chain.
Each jumper shown in Figure 2–3 is located in the JTAG DIP switch (SW3) on the back
of the board. To connect a device or interface in the chain, their corresponding switch
must be in the OFF position. Push all the switches in the ON position to only have the
FPGA in the chain. Note that the MAX V CPLD System Controller must be in the
chain to use some of the GUI interfaces.
Figure 2–3. JTAG Chain
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